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LTC3839

3839fa

APPLICATIONS INFORMATION

filter placed near the IC has been traditionally used to

reduce the effects of capacitive and inductive noise coupled

in the sense traces on the PCB. A typical filter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

This same RC filter, with minor modifications, can be

used to extract the resistive component of the current

sense signal in the presence of parasitic inductance.

For example, Figure 4a illustrates the voltage waveform

across a 2mΩ sense resistor with a 2010 footprint for a

1.2V/15A converter operating at 100% load. The waveform

is the superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

inductor ripple current and the on-time and off-time of

the top switch, the value of the parasitic inductance was

determined to be 0.5nH using the equation:

ESL

ESL(STEP)

ΔI

•

ON •tOFF

ON + tOFF

where VESL(STEP) is the voltage step caused by the ESL

and shown in Figure 4a, and tON and tOFF are top MOSFET

on-time and off-time respectively. If the RC time constant

is chosen to be close to the parasitic inductance divided by

the sense resistor (L/R), the resulting waveform looks re-

sistive again, as shown in Figure 4b. For applications using

low VSENSE(MAX), check the sense resistor manufacturer’s

data sheet for information about parasitic inductance. In

the absence of data, measure the voltage drop directly

across the sense resistor to extract the magnitude of the

ESL step and use the equation above to determine the ESL.

However, do not over filter. Keep the RC time constant less

than or equal to the inductor time constant to maintain a

high enough ripple voltage on VRSENSE.

Note that the SENSE1– and SENSE2– pins are also used

for sensing the output voltage for the adjustment of top

gate on time, tON. For this purpose, there is an additional

internal 500k resistor from each SENSE– pin to SGND,

therefore there is an impedance mismatch with their cor-

responding SENSE+ pins. The voltage drop across the

RF causes an offset in sense voltage. For example, with

RF = 100Ω, at VOUT = VSENSE– = 5V, the sense-voltage

offset VSENSE(OFFSET) = VSENSE– • RF/500k = 1mV. Such

small offset may seem harmless for current limit, but

could be significant for current reversal detection (IREV),

causing excess negative inductor current at discontinuous

mode. Also, at VSENSE(MAX) = 30mV, a mere 1mV offset

will cause a significant shift of zero-current ITH voltage

by (2.4V – 0.8V) • 1mV/30mV = 53mV. Too much shift

may not allow the output voltage to return to its regulated

value after the output is shorted due to ITH foldback.

Therefore, when a larger filter resistor RF value is used,

it is recommended to use an external 500k resistor from

each SENSE+ pin to SGND, to balance the internal 500k

resistor at its corresponding SENSE– pin.

The previous discussion generally applies to high density/

high current applications where IOUT(MAX) > 10A and low

inductor values are used. For applications where IOUT(MAX)

< 10A, set RF to 10Ω and CF to 1000pF. This will provide

a good starting point.

The filter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

Figure 4a. Voltage Waveform Measured

Directly Across the Sense Resistor

Figure 4b. Voltage Waveform Measured After the

Sense Resistor Filter. CF = 1000pF, RF = 100Ω

500ns/DIV

VSENSE

20mV/DIV

3839 F04a

VESL(STEP)

500ns/DIV

VSENSE

20mV/DIV

3839 F04b

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