LTC3880 datasheet(38/50 Pages) LINER

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LTC3839

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APPLICATIONS INFORMATION

Select the CIN capacitors to give ample capacitance and

RMS ripple current rating. Consider worst-case duty cycles

per Figure 6: If operated at steady-state with SW nodes

fully interleaved, the two channels would generate not

more than 7.5A RMS at full load. In this design example,

× 10μF ceramic capacitors are put in parallel to take the

RMS ripple current, with a 220μF aluminum-electrolytic

bulk capacitor for stability. The number of ceramic ca-

pacitors is chosen to keep the ripple current less than 3A

RMS through each device. The bulk capacitor is chosen

per manufacturer’s RMS rating based on simulation with

the circuit model provided in the CIN Selection section.

The output capacitor COUT is chosen for a low ESR to

minimize output voltage changes due to inductor ripple

current and load steps. For the worst-case output ripple

(when the two phases momentarily align and their ripples

add up), consider a single channel’s ripple current flowing

into half of the two channel’s total output capacitance:

∆VOUT(RIPPLE) = ∆IL(MAX) • ESR = 5.85A • 4.5mΩ = 26mV

However, such phase alignment typically occurs only for

several cycles during load transients. At steady load condi-

tions when the phases are interleaved, the ripple currents

from individual channels tend to cancel each other at the

output, which results in lower VOUT ripple.

Another important factor to consider is the droop caused

by load step. Here, a 10A per channel load step will cause

an output change of up to:

∆VOUT(STEP) = ∆ILOAD • ESR = 10A • 4.5mΩ = 45mV

Two optional 100μF ceramic output capacitors per channel

are included to minimize the effect of ESR and ESL in the

output ripple and to improve load step response.

The ITH compensation resistor RITH of 40k and a CITH of

220pF are chosen empirically for fast transient response,

and an additional CITH2 = 22pF is added directly from

ITH pin to SGND, to roll off the system gain at switching

frequency and attenuate high frequency noise.

To set up the detect transient (DTR) feature, pick resistors

for an equivalent RITH = RITH1//RITH2 close to the 40k. Here,

1% resistors RITH1 = 90.9k (low side) and RITH2 = 78.7k

(high side) are used, which yields an equivalent RITH of

42.2k, and a DC-bias threshold of 400mV above one-half

of INTVCC (taking into account the 5μA pull-up current

from DTR pin). This threshold can be adjusted to as low as

200mV if more sensitivity is needed (see the Load-Release

Transient Detection section). Note that even though the

accuracy of the equivalent compensation resistance RITH

is not as important, always use 1% or better resistors for

the resistor divider from INTVCC to SGND to guarantee the

relative accuracy of this DC-bias threshold. To disable the

DTR feature, simply use a single RITH resistor to SGND,

and tie the DTR pin to INTVCC.

PCB Layout Checklist

The printed circuit board layout is illustrated graphically

in Figure 14. Figure 15 illustrates the current waveforms

present in the various branches of 2-phase synchronous

regulators operating in continuous mode. Use the follow-

ing checklist to ensure proper operation:

• A multilayer printed circuit board with dedicated ground

planes is generally preferred to reduce noise coupling

and improve heat sinking. The ground plane layer

should be immediately next to the routing layer for the

power components, e.g., MOSFETs, inductors, sense

resistors, input and output capacitors etc.

• Keep SGND and PGND separate. Upon finishing the

layout, connect SGND and PGND together with a single

PCB trace underneath the IC from the SGND pin through

the exposed PGND pad to the PGND pin.

LTC3880 Datasheet(PDF) 38 Page - Linear Technology

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