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F75113 Datasheet(PDF) 21 Page - Feature Integration Technology Inc. |
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F75113 Datasheet(HTML) 21 Page - Feature Integration Technology Inc. |
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21 / 87 page  Dec,2011 V0.13P - 19 - F75113 23 GPIO1X Level / Pulse Control Register 0 0 0 0 0 0 0 0 24 GPIO1X pulse width control Register - - - - - - 0 0 25 GPIO1X internal pull-high enable Register 0 0 0 0 0 0 0 0 26 GPIO1X debounce enable Register 0 0 0 0 0 0 0 0 27 GPIO1X pin inverse enable Register 0 0 0 0 0 0 0 0 28 GPIO1X edge detect enable Register 0 0 0 0 0 0 0 0 29 GPIO1X edge detect status Register 0 0 0 0 0 0 0 0 2A SMI event of GPIO1x port enable Register 0 0 0 0 0 0 0 0 2B GPIO1X output buffer enable Register 0 0 0 0 0 0 0 0 2C GPIO1X debounce timing select Register 0 0 0 0 0 0 0 0 2D LED1X frequency select Register 0 0 0 0 0 0 0 0 2E LED1X frequency select Register 0 0 0 0 0 0 0 0 30 GPIO2X output control Register 0 0 0 0 0 0 0 0 31 GPIO2X output control Register 0 0 0 0 0 0 0 0 32 GPIO2X pin status Register - - - - - - - - 33 GPIO2X Level / Pulse Control Register 0 0 0 0 0 0 0 0 34 GPIO2X pulse width control Register - - - - - - 0 0 35 GPIO2X internal pull-high enable Register 0 0 0 0 0 0 0 0 36 GPIO2X debounce enable Register 0 0 0 0 0 0 0 0 37 GPIO2X pint inverse enable Register 0 0 0 0 0 0 0 0 38 GPIO2X edge detect enable Register 0 0 0 0 0 0 0 0 39 GPIO2X edge detect status Register 0 0 0 0 0 0 0 0 3A SMI event of GPIO2X port enable Register 0 0 0 0 0 0 0 0 3B GPIO2X output buffer enable Register 0 0 0 0 0 0 0 0 3C GPIO2X debounce timing select Register 0 0 0 0 0 0 0 0 3D LED2X frequency select Register 0 0 0 0 0 0 0 0 3E LED2X frequency select Register 0 0 0 0 0 0 0 0 3F GPIO2X low level input enable Register 0 0 0 0 0 0 0 0 40 GPIO3X output control Register 0 0 0 0 0 0 0 0 41 GPIO3X output control Register 0 0 0 0 0 0 0 0 42 GPIO3X pin status Register - - - - - - - - 43 GPIO3X Level / Pulse Control Register 0 0 0 0 0 0 0 0 44 GPIO3X pulse width control Register - - - - - - 0 0 45 GPIO3X internal pull-high enable Register 0 0 0 0 0 0 0 0 46 GPIO3X debounce enable Register 0 0 0 0 0 0 0 0 47 GPIO3X pin inverse enable Register 0 0 0 0 0 0 0 0 |
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