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F75113 Datasheet(PDF) 32 Page - Feature Integration Technology Inc. |
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F75113 Datasheet(HTML) 32 Page - Feature Integration Technology Inc. |
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32 / 87 page ![]() Dec,2011 V0.13P - 30 - F75113 2 GP02_ ENDB R/W 0 Enable GPIO02 input de-bounce with 10u (Maximum, when input signal and detected clock is synchronicity) or 25ms (Maximum, when input signal and detected clock is synchronicity) second that selected by 1Ch bit2. 1 GP01_ ENDB R/W 0 Enable GPIO01 input de-bounce with 10u (Maximum, when input signal and detected clock is synchronicity) or 25ms (Maximum, when input signal and detected clock is synchronicity) second that selected by 1Ch bit1. 0 GP00_ ENDB R/W 0 Enable GPIO00 input de-bounce with 10u (Maximum, when input signal and detected clock is synchronicity) or 25ms (Maximum, when input signal and detected clock is synchronicity) second that selected by 1Ch bit0. 8.2.19 GPIO0X Pin Inverse Enable Register ⎯ Index 17h Bit Name R/W Default Description 7 GP07_ PINV R/W 0 If the GPIO07 pin inverse was selected, the output signal would be inversed. 6 GP06_ PINV R/W 0 If the GPIO06 pin inverse was selected, the output signal would be inversed. 5 GP05_ PINV R/W 0 If the GPIO05 pin inverse was selected, the output signal would be inversed. 4 GP04_ PINV R/W 0 If the GPIO04 pin inverse was selected, the output signal would be inversed. 3 GP03_ PINV R/W 0 If the GPIO03 pin inverse was selected, the output signal would be inversed. 2 GP02_ PINV R/W 0 If the GPIO02 pin inverse was selected, the output signal would be inversed. 1 GP01_ PINV R/W 0 If the GPIO01 pin inverse was selected, the output signal would be inversed. 0 GP00_ PINV R/W 0 If the GPIO00 pin inverse was selected, the output signal would be inversed. |
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