MC34708 datasheet(107/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



107

Freescale Semiconductor

MC34708

Functional Block Description

7.9

Serial Interfaces

The IC contains a number of programmable registers for control and communication. The majority of registers are accessed

through a SPI interface in a typical application. The same register set may alternatively be accessed with an I2C interface that is

muxed on SPI pins. Table 98 describes the muxed pin options for the SPI and I2C interfaces; further details for each interface

mode follow.

7.9.1

SPI Interface

The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers, the resources of

the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on

external signals.

Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the CS

pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during

the initialization phase of a Cold Start sequence, ensuring that the I2C bus is configured before the interface is activated. With

the CS pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor due to the

integrated pull down), then the bus configuration will be latched for SPI mode.

The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The

addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy

conventions for bit positions corresponding to common functionality with previous generation FSL products.

7.9.1.1

SPI Interface Description

For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.

This is followed by one dead bit to allow for more address decode time. The MC34708 will clock the above bits in on the rising

edge of the SPI clock. The 24 data bits are then driven out on the MISO pin on the falling edge of the SPI clock, so the master

can clock them in on the rising edge of the SPI clock.

For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the

write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the

internal contents of the field addressed do not change when the 32nd CLK is sent.

tVCBL

Video Cable Detection Time (Video Cable Detection Current Source On

Time)

tRMTCON_DG Key Press Comparator Debounce Time

Table 98. SPI / I2C Bus Configuration

Pin Name

SPI Mode Functionality

I2C Mode Functionality

Configuration (69), Chip Select

Configuration (70)

CLK

SPI Clock

SCL: I2C bus clock

MISO

Master In, Slave Out (data output)

SDA: Bi-directional serial data line

MOSI

Master Out, Slave In (data input)

A0 Address Selection (71)

Notes

69.

CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.

70.

CS tied to VCOREDIG at Cold Start, configures the interface for I2C mode; the pin is not used in I2C mode, other than for configuration.

71.

In I2C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.

Table 97. USB Interface Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C  TA  85 C, unless otherwise noted. Typical values

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

Notes

MC34708 Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc

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