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SM320DM6446 Datasheet(PDF) 59 Page - Texas Instruments |
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SM320DM6446 Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 228 page  3 Device Configurations 3.1 System Module Registers 3.2 Power Considerations 3.2.1 Power Configurations at Reset SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configurations are discussed in the following sections. Table 3-1. System Module Register Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0000 PINMUX0 Pin multiplexing control 0. For details, see Section 3.5.4, PINMUX0 Register Description. 0x01C4 0004 PINMUX1 Pin multiplexing control 1. For details, see Section 3.5.5, PINMUX1 Register Description. 0x01C4 0008 DSPBOOTADDR Boot address of DSP. For details, see Section 3.3.1.2, DSPBOOTADDR Register Description. 0x01C4 000C SUSPSRC Emulator Suspend Source. For details, see Section 3.6, Emulation Control. 0x01C4 0010 INTGEN ARM/DSP Interrupt Status and Control. For details, see Section 6.7.3, ARM/DSP Communications Interrupts. 0x01C4 0014 BOOTCFG Device boot configuration. For details, see Section 3.3.1.1, BOOTCFG Register Description. 0x01C4 0018 - 0x01C4 0027 – Reserved. 0x01C4 0028 JTAGID JTAGID/Device ID number. For details, see Section 6.25.1, JTAG ID Register Description. 0x01C4 002C – Reserved. 0x01C4 0030 HPI_CTL HPI control. For details, see Section 3.5.6.10, HPI and EMIFA/ATA Pin Multiplexing. 0x01C4 0034 USBPHY_CTL USB PHY control. For details, see Section 6.15.1, USBPHY_CTL Register Description. 0x01C4 0038 CHP_SHRTSW Chip shorting switch control. For details, see Section 3.2.1, Power Configurations at Reset. 0x01C4 003C MSTPRI0 Bus master priority control 0. For details, see Section 3.5.1, Switched Central Resource (SCR) Bus Priorities. 0x01C4 0040 MSTPRI1 Bus master priority control 1. For details, see Section 3.5.1, Switched Central Resource (SCR) Bus Priorities. 0x01C4 0044 VPSS_CLKCTL VPSS clock control. 0x01C4 0048 VDD3P3V_PWDN VDD 3.3V I/O powerdown control. For details, see Section 3.2.2, Power Configurations after Reset. 0x01C4 004C DRRVTPER Enables access to the DDR2 VTP Register. 0x01C4 0050 - 0x01C4 006F – Reserved. Global device power domains are controlled by the Power and Sleep Controller, except as shown in the following sections. As described in the DM6446 Power and Clock Domains section, the DM6446 has two power domains: Always On and DSP. There is a shorting switch between the two power domains that must be opened when the DSP domain is powered off and closed when the DSP domain is powered on. The CHP_SHRTSW register, shown in Figure 3-1, controls the shorting switch between the device always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain. Submit Documentation Feedback Device Configurations 59 |
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