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SM320DM6446 Datasheet(PDF) 75 Page - Texas Instruments |
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SM320DM6446 Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 228 page  3.5.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 Table 3-22. ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS SPI_EN1/ UART_TXD1/ UART_RXD1/ ATAEN UART1 HDIREN SPI HDDIR/ DMACK DMARQ GPIO[42] 0 0 0 0 DMACK DMARQ GPIO[42] 0 0 0 1 DMACK DMARQ SPI_EN1 0 0 1 - DMACK DMARQ Driven Low 0 1 0 0 UART_TXD1 UART_RXD1 GPIO[42] 0 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1 0 1 1 - UART_TXD1 UART_RXD1 Driven Low 1 0 0 0 DMACK DMARQ GPIO[42]x 1 0 0 1 DMACK DMARQ SPI_EN1x 1 0 1 - DMACK DMARQ HDDIR 1 1 0 0 UART_TXD1 UART_RXD1 GPIO[42]x 1 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1x 1 1 1 - UART_TXD1 UART_RXD1 HDDIR Table 3-23 and Table 3-24 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled (VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] / EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address based on the AEAW value. Submit Documentation Feedback Device Configurations 75 |
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