SM320DM6446 datasheet(12/228 Pages) TI1

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2.3.12 ARM Interrupt Controller (AINTC)

2.3.13 System Module

2.3.14 Power Management

2.4 DSP Subsystem

2.4.1

C64x+ DSP CPU Description

SM320DM6446

Digital Media System-on-Chip

SPRS607A – JUNE 2009 – REVISED JUNE 2009

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The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ

(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this

document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see

Section 2.8.3, Documentation Support for the ARM Subsystem Guide.

The ARM Subsystem includes the System module. The System module consists of a set of registers for

configuring and controlling a variety of system functions. For details and register descriptions for the

System module, see Section 3, Device Configurations and see Section 2.8.3, Documentation Support, for

the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).

DM6446 has several means of managing power consumption. There is extensive use of clock gating,

which reduces the power used by global device clocks and individual peripheral clocks. Clock

management can be utilized to reduce clock frequencies in order to reduce switching power. For more

details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral

and Electrical Specifications, and see Section 2.8.3, Documentation Support, for the TMS320DM644x

ARM Subsystem Reference Guide (literature number SPRUE14).

DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to

customize an optimal power management strategy. Several typical power management scenarios are

described in the following sections.

The DSP Subsystem includes the following features:

• C64x+ DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 80KB L1 Data (L1D)/Cache (up to 32KB)

• 64KB Unified Mapped RAM/Cache (L2)

• Little endian

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two

data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain

32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be

data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit

data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are

stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or

32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one

instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units

perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from

memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with

add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four

16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for

Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and

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