SM320DM6446 datasheet(86/228 Pages) TI1

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Peripheral and Electrical Specifications

6.1 Parameter Information

6.1.1

Parameter Information Device-Specific Information

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

Ω

(see note)

Tester Pin Electronics

Data Manual Timing Reference Point

Output

Under

Test

NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the

data manual timings.

Ω

3.5 nH

Device Pin

(see note)

Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

6.1.1.1

Signal Transition Levels

Vref

Vref = VIL MAX (or VOL MAX)

Vref = VIH MIN (or VOH MIN)

SM320DM6446

Digital Media System-on-Chip

SPRS607A – JUNE 2009 – REVISED JUNE 2009

www.ti.com

Figure 6-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,

Vref = 1.5 V. For 1.8 V I/O, Vref = 0.9 V.

Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,

VOLMAX and VOH MIN for output clocks.

Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels

Peripheral and Electrical Specifications

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