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SM320DM6446 Datasheet(PDF) 68 Page - Texas Instruments |
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SM320DM6446 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 228 page  3.5 Configurations After Reset 3.5.1 Switched Central Resource (SCR) Bus Priorities SM320DM6446 Digital Media System-on-Chip SPRS607A – JUNE 2009 – REVISED JUNE 2009 www.ti.com The following sections give the details on configuring the device after reset. Prioritization within the switched central resource (SCR) is programmable for each master. The register bit fields and default priority levels for DM6446 bus masters are shown in Table 3-12. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and Figure 3-6. The C64x+, VPSS, and EDMA masters contain registers that control their own priority values. Table 3-12. DM6446 Default Bus Master Priorities BUS PRIORITY BIT FIELD MASTER DEFAULT PRIORITY LEVEL VPSSP VPSS 0 (VPSS PCR Register) EDMATC0P EDMATC0 0 (EDMACC QUEPRI Register) EDMATC1P EDMATC1 0 (EDMACC QUEPRI Register) ARM_DMAP ARM (DMA) 1 (MSTPRI0 Register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 Register) C64X+_DMAP C64X+ 7 (C64x+ MDMAARBE.PRI Register bit field) (DMA) C64X+_CFGP C64X+ 1 (MSTPRI0 Register) (CFG) EMACP EMAC 4 (MSTPRI1 Register) USBP USB 4 (MSTPRI1 Register) ATAP ATA/CF 4 (MSTPRI1 Register) VLYNQP VLYNQ 4 (MSTPRI1 Register) HPIP HPI 4 (MSTPRI1 Register) Figure 3-5. MSTPRI0 Register 31 19 18 16 RESERVED VICPP(1) R-0000 0000 0000 0 R/W-101 15 11 10 8 7 6 4 3 2 0 RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001 LEGEND: R = Read; W = Write; -n = value after reset (1) The VICPP bit field is configured by the third-party software. When modifying the MSTPRI0 register a read/modify/write must be performed to preserve the configuration set by the third-party software. Figure 3-6. MSTPRI1 Register 31 23 22 20 19 18 16 RESERVED HPIP RSV VLYNQP R-0000 0000 0 R-100 R-0 R/W-100 15 14 12 11 10 8 7 6 4 3 2 0 RSV ATAP RSV USBP RSV RESERVED RSV EMACP R-0 R/W-100 R-0 R/W-100 R-0 R-100 R-0 R/W-100 LEGEND: R = Read; W = Write; -n = value after reset Device Configurations 68 Submit Documentation Feedback |
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