SM320DM6446 datasheet(74/228 Pages) TI1

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3.5.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

SM320DM6446

Digital Media System-on-Chip

SPRS607A – JUNE 2009 – REVISED JUNE 2009

www.ti.com

GPIO[4]

GPIO[3]

Table 3-20. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS

MULTIPLEXED PINS

R1/

B1/

G1/

G0/

RGB888

PWM2

PWM1

CFLDEN

LFLDEN

GPIO[38]

GPIO[6]

GPIO[5]

GPIO[2]

GPIO[38]

GPIO[6]

GPIO[5]

GPIO[2]

The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-21. If ATA pin

functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and

control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only

allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in

conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1

if the buffer is not being used (i.e. for Compact Flash). This multiplexing is shown in Table 3-22. When

ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be

used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA

buffers drive away from DM644X and don’t cause bus contention with the EMIFA. Note that switching

between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus

contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA

requests have completed before clearing the ATAEN bit.

Table 3-21. ATA, EMIFA, and GPIO Pin Multiplexing Control(1)

PINMUX0

MULTIPLEXED PINS

BIT FIELD

EM_BA[1]/

EM_A[0]/

EM_D[15:0]/

GPIO[50]/

GPIO[51]/

EM_R/W

EM_BA[0]/

EM_WAIT/

DIOR/

DIOW/

ATAEN

GPIO[52]/

GPIO[53]/

DD[15:0]

ATA_CS0

ATA_CS1

INTRQ

ATA0

IORDY

EM_OE

EM_WE

ATA1

ATA2

GPIO[50]

GPIO[51]

EM_R/W

EM_BA[0]

EM_WAIT

EM_OE

EM_WE

EM_BA[1]/

EM_A[0]/

EM_D[15:0]

GPIO[52](2)

GPIO[53](2)

ATA_CS0

ATA_CS1

INTRQ

ATA0

IORDY

DIOR

DIOW

ATA1

ATA2

DD[15:0]

(1)

This table assumes that the HPIEN bit in the PINMUX0 register is "0".

(2)

This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

Device Configurations

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