LPC4088 datasheet(38/123 Pages) NXP

38 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

38 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[1]

PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating

pins, if not used, should be tied to ground or power to minimize power consumption.

[2]

I = Input; O = Output; G = Ground; S = Supply.

[3]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[4]

5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with

TTL levels and hysteresis. This pad can be powered by VBAT.

[5]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital

section of the pad is disabled.

[6]

5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL

levels and hysteresis.

[7]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[8]

Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[9]

Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

VREFP

ADC positive reference voltage: This should be the same

voltage as VDDA, but should be isolated to minimize noise

and error. The voltage level on this pin is used as a

reference for ADC and DAC. Tie this pin to 3.3 V if the

ADC and DAC are not used.

VSS

33,

63,

77,

93,

114,

133,

148,

169,

189,

200

L3,

T5,

R9,

P12,

N16,

H14,

E15,

A12,

B6,

H4,

P4,

L9,

L13,

G13,

D13,

C11,

44,

65,

79,

103,

117,

139

24,

43,

57,

Ground: 0 V reference for digital IO pins.

VSSREG

32,

84,

172

D12,

K4,

P10

H3,

L8,

A10

22,

59,

119

33,

Ground: 0 V reference for internal logic.

VSSA

Analog ground: 0 V power supply and reference for the

ADC and DAC. This should be the same voltage as VSS,

but should be isolated to minimize noise and error.

XTAL1

[14]

[16]

Input to the oscillator circuit and internal clock generator

circuits.

XTAL2

[14]

[16]

Output from the oscillator amplifier.

Table 3.

Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5

(EMC pins).

Symbol

Description

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