LPC4088 datasheet(64/123 Pages) NXP

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LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

64 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

On wake-up from Deep-sleep mode, the code execution and peripherals activities will

resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If

the main external oscillator was used, the code execution will resume when 4096 cycles

expire. PLL and clock dividers need to be reconfigured accordingly.

7.36.4.3

Power-down mode

Power-down mode does everything that Deep-sleep mode does but also turns off the

power to the IRC oscillator and the flash memory. This saves more power but requires

waiting for resumption of flash operation before execution of code or data access in the

flash memory can be accomplished.

When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are

stopped. The RTC remains running if it has been enabled and RTC interrupts may be

used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are

automatically turned off and the clock selection multiplexers are set to use the system

clock sysclk (the reset state). The clock divider control registers are automatically reset to

zero. If the Watchdog timer is running, it will continue running in Power-down mode.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60

s to start-up. After this four IRC cycles will expire before the

code execution can then be resumed if the code was running from SRAM. In the

meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the

100

s flash start-up time. When it times out, access to the flash will be allowed. Users

need to reconfigure the PLL and clock dividers accordingly.

7.36.4.4

Deep power-down mode

The Deep power-down mode can only be entered from the RTC block. In Deep

power-down mode, power is shut off to the entire chip with the exception of the RTC

module and the RESET pin.

To optimize power conservation, the user has the additional option of turning off or

retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn

off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the

VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before

device operation can be restarted.

The LPC408x/7x can wake up from Deep power-down mode via the RESET pin or an

alarm match event of the RTC.

7.36.4.5

Wake-up Interrupt Controller (WIC)

The WIC allows the CPU to automatically wake up from any enabled priority interrupt that

can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep

power-down modes.

The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When

the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a

mask of the current interrupt situation to the WIC.This mask includes all of the interrupts

that are both enabled and of sufficient priority to be serviced immediately. With this

information, the WIC simply notices when one of the interrupts has occurred and then it

wakes up the CPU.

The WIC eliminates the need to periodically wake up the CPU and poll the interrupts

resulting in additional power savings.

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