SPC564B74L7 datasheet(79/118 Pages) STMICROELECTRONICS

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SPC564Bxx - SPC56ECxx

Electrical Characteristics

Doc ID 17478 Rev 4

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4.14

FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to

generate a fast system clock from the main oscillator driver.

4.15

Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz main internal RC oscillator. This is used as the default clock

at the power-up of the device and can also be used as input to PLL.

ISXOSC

CC T

Slow external crystal oscillator

consumption

——

—

µA

TSXOSCSU CC T

Slow external crystal oscillator

start-up time

——

—

2(3)

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

All values need to be confirmed during device validation.

Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

Table 38.

Slow external crystal oscillator (32 kHz) electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

Table 39.

FMPLL electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

fPLLIN

SR — FMPLL reference clock(3)

—4

—

MHz

ΔPLLIN SR —

FMPLL reference clock duty

cycle(3)

—40

—

fPLLOUT CC P

FMPLL output clock

frequency

—

120

MHz

fCPU

SR — System clock frequency

—

120 + 2%(4) MHz

fFREE

CC P Free-running frequency

—

150

MHz

tLOCK

CC P FMPLL lock time

Stable oscillator (fPLLIN = 16

MHz)

100

µs

ΔtLTJIT CC — FMPLL long term jitter

fPLLIN = 40 MHz (resonator),

fPLLCLK @ 120 MHz, 4000

cycles

——

(for < 1ppm)

IPLL

CC C FMPLL consumption

TA = 25 °C

—

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

All values need to be confirmed during device validation.

PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used

in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.

fCPU 120 + 2% MHz can be achieved at 125 °C.

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