SPC564B74L7 datasheet(50/118 Pages) STMICROELECTRONICS

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Electrical Characteristics

SPC564Bxx - SPC56ECxx

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Doc ID 17478 Rev 4

Note:

Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability. During overload conditions (VIN > VDD_HV_A/HV_B or

VIN <VSS_HV), the voltage on pins with respect to ground (VSS_HV) must not exceed the

recommended values.

VRC_CTRL

(2)

Base control voltage for

external BCP68 NPN device

Relative to VDD_LV

0VDD_LV +1

VSS_ADC

Voltage on VSS_HV_ADC0,

VSS_HV_ADC1 (ADC

reference) pin with respect to

ground (VSS_HV)

—VSS_HV − 0.1

VSS_HV +0.1

VDD_HV_ADC0 SR

Voltage on VDD_HV_ADC0

with respect to ground

(VSS_HV)

—–0.3

6.0

Relative to VDD_HV_A

(3)

VDD_HV_A − 0.3 VDD_HV_A+0.3

VDD_HV_ADC1

(4)

Voltage on VDD_HV_ADC1

with respect to ground

(VSS_HV)

—–0.3

6.0

Relative to VDD_HV_A

(2)

VDD_HV_A−0.3

VDD_HV_A+0.3

VIN

Voltage on any GPIO pin with

respect to ground (VSS_HV)

Relative to

VDD_HV_A/HV_B

−0.3

VDD_HV_A/HV_B

+0.3

IINJPAD

Injected input current on any

pin during overload condition

—

–10

IINJSUM

Absolute sum of all injected

input currents during overload

condition

—

–50

IAVGSEG

(5)

Sum of all the static I/O

current within a supply

segment

(VDD_HV_A or VDD_HV_B)

VDD = 5.0 V ± 10%,

PAD3V5V = 0

VDD = 3.3 V ± 10%,

PAD3V5V = 1

TSTORAGE

SR Storage temperature

—

–55(6)

150

°C

VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust

against any supply order.

This voltage is internally generated by the device and no external voltage should be supplied.

Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is

6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.

PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be

within ±300 mV of VDD_HV_B when these channels are used for ADC_1.

Any temperature beyond 125 °C should limit the current to 50 mA (max).

This is the storage temperature for the flash memory.

Table 9.

Absolute maximum ratings (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

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