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SPC564B74L7 Datasheet(PDF) 97 Page - STMicroelectronics |
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SPC564B74L7 Datasheet(HTML) 97 Page - STMicroelectronics |
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97 / 118 page ![]() SPC564Bxx - SPC56ECxx Electrical Characteristics Doc ID 17478 Rev 4 97/118 — Slave Hold Time (SS active to SCK hold time) tHSS 10 — ns 5 Slave Access Time (SS active to SOUT valid)(4) tA — 42 ns 6 Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) tDIS — 25 ns 7 CSx to PCSS time tPCSC 0— ns 8PCSS to PCSx time tPASC 0— ns 9 Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)(5) Master (MTFE = 1, CPHA = 1) tSUI 36 5 36 36 — — — — ns ns ns ns 10 Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)(5) Master (MTFE = 1, CPHA = 1) tHI 0 4 0 0 — — — — ns ns ns ns 11 Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tSUO — — — — 12 37 12 12 ns ns ns ns 12 Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tHO 0(6) 9.5 0(7) 0(8) — — — — ns ns ns ns 1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this table. 2. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For SPC564B74 and SPC56EC74, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > Δt CSC . 3. The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For SPC564B74 and SPC56EC74, the spec value of tASC will be attained only if TDSPI x PASC x ASC > Δt ASC. 4. The parameter value is obtained from tSUSS and tSUO for slave. 5. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00. 6. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is −2 ns. 7. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is −2 n. 8. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is −2 ns. Table 50. DSPI timing (continued) Spec Characteristic Symbol Unit Min Max |
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