WM8988 datasheet(34/56 Pages) WOLFSON

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WM8988

Production Data

PD, Rev 4.0, October 2008

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data into the WM8988 and outputting ADC data

from it. It uses four pins:

•

ADCDAT: ADC data output

•

DACDAT: DAC data input

•

LRC: DAC and ADC data alignment clock

•

BCLK: Bit clock, for synchronisation

The clock signals BCLK and LRC can be an output when the WM8988 operates as a master, or an

input when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:

•

Left justified

•

DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8988 can be configured as either a master or slave mode device. As a master device the

WM8988 generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer

on ADCDAT and DACDAT. In slave mode, the WM8988 responds with data to clocks it receives over

the digital audio interface. The mode can be selected by writing to the MS bit (see Table 23). Master

and slave modes are illustrated below.

Figure 10 Master Mode

Figure 11 Slave Mode

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 12 Left Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

WM8988 Datasheet(PDF) 34 Page - Wolfson Microelectronics plc