WM8988 datasheet(37/56 Pages) WOLFSON

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Production Data

WM8988

PD, Rev 4.0, October 2008

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in

Table 31. MS selects audio interface operation in master or slave mode. In Master mode BCLK and

LRC are outputs. The frequency of LRC is set by the sample rate control bits SR[4:0] and USB. In

Slave mode BCLK and LRC are inputs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

BCLKINV

BCLK invert bit (for master and slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

LRSWAP

Left/Right channel swap

1 = swap left and right DAC data in

audio interface

0 = output left and right data as normal

right, left and i2s modes – LRCLK

polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

LRP

DSP Mode – mode A/B select

1 = MSB is available on 1

st BCLK rising

edge after LRC rising edge (mode B)

0 = MSB is available on 2

nd BCLK rising

edge after LRC rising edge (mode A)

3:2

WL[1:0]

Audio Data Word Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

R7 (07h)

Digital Audio

Interface

Format

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode

10 = I

2S Format

01 = Left justified

00 = reserved (do not use this setting)

Table 31 Audio Data Format Control

AUDIO INTERFACE OUTPUT TRISTATE

DACLRC and BCLK to inputs. In Slave mode (MASTER=0) LRC and BCLK are by default configured

as inputs and only ADCDAT will be tri-stated, (see Table 32).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

TRI

Tristates ADCDAT and switches ADCLRC,

DACLRC and BCLK to inputs.

0 = ADCDAT is an output, LRC and BCLK are

inputs (slave mode) or outputs (master mode)

1 = ADCDAT is tristated, LRC and BCLK are

inputs

Table 32 Tri-stating the Audio Interface

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