WM8988 datasheet(44/56 Pages) WOLFSON

44 / 56 page

WM8988

Production Data

PD, Rev 4.0, October 2008

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8988, the master clock may be

stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.

However, since setting DIGENB has no effect on the power consumption of other system

components external to the WM8988, it is preferable to disable the master clock at its source

wherever possible.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 40 ADC and DAC Oversampling Rate Selection

NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set

to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may

prevent DACs and ADCs from re-starting correctly.

SAVING POWER BY REDUCING BIAS CURRENTS

The design of the DAC allows user trade-off between power consumption and performance, using

the DACMIXBIAS bit. The default setting (DACMIXBIAS=0) delivers the best audio performance.

Setting DACMIXBIAS=1 reduces AVDD current consumption, at the cost of marginally reduced

performance (see “Electrical Characteristics” for details).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R67 (43h)

DACMIX

BIAS

DAC biasing

0 = high bias current (results in higher

performance and power consumption)

1 = low bias current (results in lower

performance and power consumption)

Table 41 DAC Biasing

SAVING POWER BY REDUCING OVERSAMPLING RATE

The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.

Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in

a slight decrease in noise performance but will also reduce the power consumption of the device. In

USB mode ADCOSR must be set to 0, i.e. 128x oversampling.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADCOSR

ADC oversample rate select

1 = 64x (lowest power)

0 = 128x (best SNR)

R24 (18h)

Additional Control

(2)

DACOSR

DAC oversample rate select

1 = 64x (lowest power)

0 = 128x (best SNR)

Table 42 ADC and DAC Oversampling Rate Selection

ADCOSR set to ‘1’, 64x oversample mode, is not supported in USB mode (USB=1).

WM8988 Datasheet(PDF) 44 Page - Wolfson Microelectronics plc

WM8988 Datasheet(HTML) 44 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL