WM8311 datasheet(128/302 Pages) WOLFSON

128 / 302 page

WM8311

Pre-Production

PP, May 2012, Rev 3.1

128

18.5 AUXADC INTERRUPTS

The AUXADC is associated with a number of Interrupt event flags to indicate when new AUXADC

data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed.

Each of these secondary interrupts triggers a primary AUXADC Interrupt, AUXADC_INT (see

Section 23). This can be masked by setting the mask bit(s) as described in Table 68.

Note that AUXADC_DATA_EINT is not cleared by reading the measured AUXADC data, it can only

be cleared by writing ‘1’ to the AUXADC_DATA_EINT register.

The AUXADC interrupts can be programmed using bits in Table 68.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

AUXADC_DATA_EINT

AUXADC Data Ready interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

7:4

AUXADC_DCOMPn_EINT

AUXADC Digital Comparator n interrupt

(Trigger is controlled by DCMPn_GT)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_AUXADC_DATA_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

7:4

IM_AUXADC_DCOMPn_EI

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Note: n is a number between 1 and 4 that identifies the individual Comparator.

Table 68 AUXADC Interrupts

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