WM8311 datasheet(163/302 Pages) WOLFSON

163 / 302 page

Pre-Production

WM8311

PP, May 2012, Rev 3.1

163

ADDRESS

BIT

LABEL

DESCRIPTION

R16404

(4014h)

Interrupt Status

HC_DC2_EINT

DC-DC2 High Current interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

HC_DC1_EINT

DC-DC1 High Current interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16412

(401Ch)

Interrupt Status

4 Mask

IM_HC_DC2_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_HC_DC1_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 104 Overcurrent Interrupts

23.2.16 UNDERVOLTAGE INTERRUPTS

The primary UV_INT interrupt comprises fourteen secondary interrupts as described in

Section 15.13). The secondary interrupt bits are defined in Table 105.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403

(4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary

interrupts are all masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16403

(4013h)

Interrupt Status

9:0

UV_LDOn_EINT

LDOn Undervoltage interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16404

(4014h)

Interrupt Status

3:0

UV_DCm_EINT

DC-DCm Undervoltage interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16411

(401Bh)

Interrupt Status

3 Mask

9:0

IM_UV_LDOn_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

R16412

(401Ch)

Interrupt Status

4 Mask

3:0

IM_UV_DCm_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Notes:

n is a number (1-5, 7) that identifies the individual LDO Regulator.

m is a number between 1 and 4 that identifies the individual DC-DC Converter.

Table 105 Undervoltage Interrupts

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