WM8311 datasheet(160/302 Pages) WOLFSON

160 / 302 page

WM8311

Pre-Production

PP, May 2012, Rev 3.1

160

23.2.10 CURRENT SINK INTERRUPTS

The primary CS_INT interrupt comprises two secondary interrupts as described in Section 16.3. The

secondary interrupt bits are defined in Table 100.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a CS_INT interrupt. The secondary interrupt bits in R16402

(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

CS2_EINT

Current Sink 2 interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

CS1_EINT

Current Sink 1 interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_CS2_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_CS1_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 100 Current Sink Interrupts

23.2.11 REAL TIME CLOCK INTERRUPTS

The primary RTC_INT interrupt comprises two secondary interrupts as described in Section 20.3. The

secondary interrupt bits are defined in Table 101.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401

(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

RTC_PER_EINT

RTC Periodic interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

RTC_ALM_EINT

RTC Alarm interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_RTC_PER_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_RTC_ALM_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 101 Real Time Clock (RTC) Interrupts

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