WM8311 datasheet(158/302 Pages) WOLFSON

158 / 302 page

WM8311

Pre-Production

PP, May 2012, Rev 3.1

158

23.2.6 TOUCH PANEL DATA INTERRUPTS

The primary TCHDATA_INT interrupt comprises a single secondary interrupt as described in

Section 19.5. The secondary interrupt bits are defined in Table 96.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a TCHDATA_INT interrupt. The secondary interrupt bit in R16401

(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by

default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

TCHDATA_EINT

Touch panel Data interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_TCHDATA_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 96 Touch Panel Data Interrupts

23.2.7 TOUCH PANEL PEN DOWN INTERRUPTS

The primary TCHPD_INT interrupt comprises a single secondary interrupt as described in

Section 19.5. The secondary interrupt bits are defined in Table 97.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a TCHPD_INT interrupt. The secondary interrupt bit in R16401

(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by

default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

TCHPD_EINT

Touch panel Pen Down interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_TCHPD_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 97 Touch Panel Pen Down Interrupts

23.2.8 AUXADC INTERRUPTS

The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5.

The secondary interrupt bits are defined in Table 98.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in

R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all

masked by default.

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