WM8311 datasheet(156/302 Pages) WOLFSON

156 / 302 page

WM8311

Pre-Production

PP, May 2012, Rev 3.1

156

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

PS_POR_EINT

Power On Reset interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PS_SLEEP_OFF_EINT

SLEEP or OFF interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PS_ON_WAKE_EINT

ON or WAKE interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_PS_POR_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PS_SLEEP_OFF_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PS_ON_WAKE_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 91 Power State Interrupts

23.2.2 THERMAL INTERRUPTS

The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26.

The secondary interrupt bit is defined in Table 92.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h)

is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

TEMP_THW_CINT

Thermal Warning interrupt

(Rising and Falling Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(4019h)

Interrupt Status

1 Mask

IM_TEMP_THW_CINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 92 Thermal Interrupts

23.2.3 GPIO INTERRUPTS

The primary GP_INT interrupt comprises sixteen secondary interrupts as described in Section 21.4.

The secondary interrupt bits are defined in Table 93.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405

(4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

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