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WM8311 Datasheet(PDF) 157 Page - Wolfson Microelectronics plc |
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WM8311 Datasheet(HTML) 157 Page - Wolfson Microelectronics plc |
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157 / 302 page ![]() Pre-Production WM8311 w PP, May 2012, Rev 3.1 157 ADDRESS BIT LABEL DESCRIPTION R16405 (4015h) Interrupt Status 5 15:0 GPn_EINT GPIO interrupt. (Trigger is controlled by GPn_INT_MODE) Note: Cleared when a ‘1’ is written. R16413 (401Dh) Interrupt Status 5 Mask 15:0 IM_GPn_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 16 that identifies the individual GPIO. Table 93 GPIO Interrupts 23.2.4 ON PIN INTERRUPTS The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in Section 11.6. The secondary interrupt bit is defined in Table 94. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS BIT LABEL DESCRIPTION R16401 (4011h) Interrupt Status 1 12 ON_PIN_CINT ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. R16409 (4019h) Interrupt Status 1 Mask 12 IM_ON_PIN_CINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 94 ON Pin Interrupt 23.2.5 WATCHDOG INTERRUPTS The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25. The secondary interrupt bits are defined in Table 95. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS BIT LABEL DESCRIPTION R16401 (4011h) Interrupt Status 1 11 WDOG_TO_EINT Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16409 (4019h) Interrupt Status 1 Mask 11 IM_WDOG_TO_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 95 Watchdog Timer Interrupts |
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