WM8311 datasheet(155/302 Pages) WOLFSON

155 / 302 page

Pre-Production

WM8311

PP, May 2012, Rev 3.1

155

ADDRESS

BIT

LABEL

DESCRIPTION

1 = Mask interrupt.

Default value is 1 (masked)

IM_AUXADC_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PPM_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_CS_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_RTC_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_OTP_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_CHG_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_HC_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_UV_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 90 Primary Interrupt Status and Mask Bits

23.2 SECONDARY INTERRUPTS

The following sections define the secondary interrupt status and control bits associated with each of

the primary interrupt bits defined in Table 90.

23.2.1 POWER STATE INTERRUPT

The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The

secondary interrupt bits are defined in Table 91.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402

(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

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