WM8326 datasheet(128/255 Pages) WOLFSON

128 / 255 page

WM8326

Production Data

PD, June 2012, Rev 4.0

128

23.2.11 UNDERVOLTAGE INTERRUPTS

The primary UV_INT interrupt comprises fourteen secondary interrupts as described in

Section 15.12). The secondary interrupt bits are defined in Table 75.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403

(4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary

interrupts are all masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16403

(4013h)

Interrupt Status

9:0

UV_LDOn_EINT

LDOn Undervoltage interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16404

(4014h)

Interrupt Status

3:0

UV_DCm_EINT

DC-DCm Undervoltage interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16411

(401Bh)

Interrupt Status

3 Mask

9:0

IM_UV_LDOn_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

R16412

(401Ch)

Interrupt Status

4 Mask

3:0

IM_UV_DCm_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Notes:

n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1-LDO10).

m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC1-DC4).

Table 75 Undervoltage Interrupts

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