SC531 datasheet(9/15 Pages) SEMTECH

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SC531

Applications Information

up resistance of 3.3 kΩ to V

CC. If the BLANKB pin is not held

low, then the output of the current limit comparator will

be determined by the CSENSE and DAC voltages. If the

DAC voltage is greater than CSENSE then the output of

the comparator will be low. If the CSENSE voltage is

greater than the DAC voltage then the output of the com-

parator will go high causing the CLF flag to go high and

OUT and OUT2 to be driven low. This event is latched

and will not be released until CSENSE goes below DAC

and the IN pin goes from low to high.

SPI Interface

A write sequence begins by bringing CSB low. Once CSB

is low, the data on the DIN line is clocked into the 6-bit

shift register on the falling edges of CLK. On the 6th

falling clock edge, the last data bit is clocked in and the

DAC is updated. CSB can be held low or high at this point

and any data or clock pulses following the 6th falling

clock edge are ignored. CSB must be brought high for the

minimum specified time before the next write sequence is

initiated with the falling edge of CSB. Figure 3 shows the

Serial Timing Diagram and Figure 4 shows the Input

ZVS Comparator

The ZVS comparator is a current-input (Norton) compara-

tor that provides information that the ZVS condition has

been reached by comparing the LX node to HV

IN. The

falling edge of the power FET LX node going below HV

(ZVS output going low) is the faster edge. The structure of

the comparator allows fast detection with a large voltage

range. Series resistors are placed from LX to ZVSP and

IN to ZVSN. The resistor value should be chosen based

on the voltage levels that are being compared and should

be optimized to produce input currents in the 0-40μA

range. The ZVSP and ZVSN pins can vary from 2-4V based

on this normal input current range.

The ZVSN and ZSVP input pins can tolerate currents up to

300μA, but the accuracy and speed specifications are only

valid in the 0-40μA range.

Gate Drivers 1 and 2

The high-current output stage in the SC53 is capable of

providing 2A source, 4A sink peak current and voltage

swings from PVDD to PGND for both OUT and OUT2.

These outputs can drive individual power FETs which can

be used in parallel or can be combined to drive one larger

device. The second output (OUT2) can be disabled to save

power by setting OE2B input to a logic high. If OE2B is set

high during normal switching operation, the OUT2 output

is not disabled until the next falling edge of IN.

The driver outputs follow the state of the IN pin. When IN

is high OUT and OUT2 (if OE2B is low) are high. The

outputs will be pulled low when IN goes low or when the

current limit is reached.

Reference Divider, Buffer, DAC, and Current

Limit Comparator

The SC53 contains a reference divider, buffer, DAC, and

current limit comparator that combine to provide a high-

speed and high-accuracy programmable current limit.

The reference voltage is generated by a resistive divide by

four from VREFH to VREFL. This voltage is referenced at

the VREF pin. Alternatively, an external reference can drive

the VREF pin if a different value is desired. The equation

for the VREF voltage is shown below.

The VREFL input must be within +/-300mV of the GND pin

and is typically connected to analog ground.

The VREF voltage is buffered and then used as the refer-

ence for the 8-bit DAC. The 8-bit DAC is controlled by the

SPI (see next section for protocol information). The output

of the DAC connects to the DAC pin and to the negative

input of the current limit comparator.

The positive input of the current limit comparator is con-

nected to the CSENSE pin through blanking circuitry.

When the BLANKB pin is held low the CSENSE pin is dis-

connected from the comparator and the positive input is

shorted to ground. The BLANKB pin has an internal pull-

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