SC531

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Applications Information (continued)

Gate Driver 3

Gate Driver 3 is a third auxiliary gate drive that is controlled

by the IN3 pin, an independent input. It has a separate

power supply (PVDD3) and ground (PGND3) connection.

The output OUT3 is 2A source, 4A sink capable. This

output can be used as a general purpose driver which can

be used to drive the FET for an active clamp or active

snubber. Other uses include driving the FET for soft-

switching ZVT or to drive a secondary PWM output.

Applications

The SC53 is suited for applications which contain a micro-

controller or DSP to control PWM switching. The auxiliary

OUT3 output and the DAC controlled current limit can be

used to implement a variety of switching topologies.

By driving the IN3 input with a signal that is inverted from

the IN input, the OUT3 driver can be used to drive an

external P-channel FET for an active clamp converter. In

addition, the DAC can be programmed to vary in real-time

as a function of the main error voltage from the system

microcontroller. This causes each OUT/2 pulse to termi-

nate when the peak current reaches the real-time DAC

setting, resulting in current-mode operation. Combining

the DAC control with the external P-channel FET circuitry

results in an Active Clamp Current Mode Converter. Refer

to Figure .

The above converter can also be used to provide a pro-

grammable constant current output by setting the DAC to

a constant value. The IN input has a longer duty cycle than

is required to maintain the output, but each OUT/2 pulse

is terminated early by the current limit function. The

average current to the load will equal the peak inductor

current reduced by 50% of the inductor ripple current.

The OUT3 output can be used to drive the FET for a ZVT

switch such as is used in PFC boost converters. The ZVS

comparator can be used to detect when the ZVT FET has

completed its discharge of the main FET by connecting

two additional resistors to the ZVS inputs, R

resistors RZ3 and RZ4 should be selected to keep the keep

the ZVSP/N input current below 300uA at maximum VIN.

Refer to Figure 2.

PCB Layout Guidelines

Any switch-mode converter requires a good PCB layout to

achieve best performance. The following guidelines

should be followed to produce an optimum PCB layout.

All bypass capacitors should be located close to the pins

which they connect to. Use short, direct copper traces to

connect between the capacitor and the IC pins. Bypass

capacitors should be placed on the same side of the PCB

The pins which require bypass capacitors are shown

below:

VCC, GND

PVDD, PGND

PVDD2, PGND2

PVDD3, PGND3

The connections between the PGND pins and the power

FETs should be short and direct, using a ground plane if

available. If vias are required use multiple vias to reduce

impedance between the IC and the FETs. The gate traces

should be short and direct. Use wide, short gate traces to

reduce susceptibility to noise generated by nearby FET

switching. The gate trace routings should avoid any of the

FET drain nodes.

The CSENSE signal should be referenced to GND (analog

ground). A capacitor on the CSENSE input should be

located near the CSENSE pin and connected to GND, and

connected to the IC with short direct traces.

Any VREFH, VREFL, or VREF bypass capacitors should be

placed close to the pins, routed with direct traces, and

connected to GND.

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