AD1846

REV. A

–19–

Test and Initialization Register (IXA3:0 = 11)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1 1

COR

PUR

ACI

DRS

ORR1

ORR0

ORL1

ORL0

ORL1:0

Overrange Left Detect. These bits indicate the overrange on the left input channel. This bit changes on a sample-by-

sample basis. This bit is read only.

0

Less than –1 dB underrange

1

Between –1 dB and 0 dB underrange

2

Between 0 dB and +1 dB overrange

3

Greater than +1 dB overrange

ORR1:0

Overrange Right Detect. These bits indicate the overrange on the right input channel. This bit changes on a sample-by-

sample basis. This bit is read only.

0

Less than –1 dB underrange

1

Between –1 dB and 0 dB underrange

2

Between 0 dB and +1 dB overrange

3

Greater than +1 dB overrange

DRS

Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1846.

0

CDRQ and PDRQ are presently inactive (LO)

1

CDRQ or PDRQ are presently active (HI)

ACI

Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change Enable

(MCE). This bit is read only.

0

Autocalibration is not in progress

1

Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods

PUR

Playback Underrun. This bit is set when playback data has not arrived from the host in time to be played. As a result, a

midscale value will be sent to the DACs. This bit changes on a sample by sample basis.

COR

Capture Overrun. This bit is set when the capture data has not been read by the host before the next sample arrives. The

sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on a

sample by sample basis.

The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit

is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while checking

other status bits.

This register’s initial state after reset is “0000 0000.”

Miscellaneous Control Register (IXA3:0 = 12)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1 2

res

res

res

res

ID3

ID2

ID1

ID0

res

Reserved for future expansion. The bits are read only. Do not write to these bits.

ID3:0

AD1846 Revision ID. These four bits define the revision level of the AD1846. The AD1846 is designated

ID = “1010.” Revisions increment by one LSB. These bits are read only.

This register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use.