AD1846 datasheet(22/28 Pages) AD

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AD1846

REV. A

–22–

CDRQ/

PDRQ

OUTPUTS

CS INPUT

PDAK

INPUT

DATA7:0

INPUTS

WR INPUT

DBEN

OUTPUT

ADR1:0

INPUTS

DBDL

ADSU

CSHD

DHD2

ADHD

SUDK2

DBDIR

OUTPUT

SUDK1

CSSU

STW

WDSU

Figure 12. Control Register/PIO Write Cycle

Direct Memory Access (DMA) Transfers

The second type of bus cycle supported by the AD1846 are

DMA transfers. Both dual channel and single channel DMA op-

erations are supported. To enable Playback DMA transfers,

playback enable (PEN) must be set and PPIO cleared. To en-

able Capture DMA transfers, capture enable (CEN) must be set

and CPIO cleared. During DMA transfers, the AD1846 asserts

HI the Capture Data Request (CDRQ) or the Playback Data

Request (PDRQ) followed by the host’s asserting LO the DMA

Capture Data Acknowledge (CDAK) or Playback Data Ac-

knowledge (PDAK), respectively. The host’s asserted Acknowl-

edge signals cause the AD1846 to perform DMA transfers. The

input address lines, ADR1:0, are ignored. Data is transferred

between the proper internal sample registers.

The read strobe (RD) and write strobe (WR) delimit valid data

for DMA transfers. Chip select (CS) is a “don’t care”; its state

is ignored by the AD1846.

The AD1846 asserts the Data Request signals, CDRQ and

PDRQ, at the rate of once per sample period. PDRQ is asserted

near the beginning of an internal sample period and CDRQ is

asserted late in the same period to maximize the available pro-

cessing time. Once asserted, these signals will remain active HI

until the corresponding DMA cycle occurs with the host’s Data

Acknowledge signals. The Data Request signals will be

deasserted after the falling edge of the final RD or WD strobe in

the transfer of a sample, which typically consists of multiple

bytes. See “Data Ordering” above for a definition of “sample.”

DMA transfers may he independently aborted by resetting the

Capture Enable (CEN) and/or Playback Enable (PEN) bits in

the Interface Configuration Register. The current capture

sample transfer will be completed if a capture DMA is termi-

nated. The current playback sample transfer must be completed

if a playback DMA is terminated. If CDRQ and/or PDRQ are

asserted HI while the host is resetting CEN and/or PEN, the re-

quest must be acknowledged. The host must assert CDAK and/

or PDAK LO and complete a final sample transfer.

Single-Channel DMA

Single-Channel DMA mode allows the AD1846 to be used in

systems with only a single DMA channel. It is enabled by setting

the SDC bit in the Interface Configuration Register. All cap-

tures and playbacks take place on the playback channel. Obvi-

ously, the AD1846 cannot perform a simultaneous capture and

playback in Single-Channel DMA mode.

Playback will occur in single-channel DMA mode exactly as it

does in Two-Channel mode. Capture, however, is diverted to

the playback channel which means that the capture data request

occurs on the PDRQ pin and the capture data acknowledge

must be received on the PDAK pin. The CDRQ pin will remain

inactive LO. Any inputs to CDAK will be ignored.

Playback and capture are distinguished in Single-Channel DMA

mode by the state of the playback enable (PEN) or capture

enable (CEN) control bits. If both PEN and CEN are set in

Single-Channel DMA mode, playback will be presumed.

To avoid confusion of the origin of a request when switching be-

tween playback and capture in Single-Channel DMA mode,

both CEN and PEN should be disabled and all pending re-

quests serviced before enabling the alternative enable bit.

Switching between playback and capture in Single-Channel

DMA mode does not require changing the PPIO and CPIO bits

or passing through the Mode Change Enable state except for

initial setup. For setup, assign zeros to both PPIO and CPIO.

This configures both playback and capture for DMA. Then,

switching between playback and capture can be effected entirely

by setting and clearing the PEN and CEN control bits, a tech-

nique which avoids having to enter the Mode Change Enable

state.

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