AD1848K

REV. 0

–12–

Direct Control Register Definitions

Index Register (ADR1:0 = 0)

ADR1:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

INIT

MCE

TRD

res

IXA3

IXA2

IXA1

IXA0

IXA3:0

Index Address. These bits define the address of the AD1848K register accessed by the Indexed Data Register. These bits

are read/write.

res

Reserved for future expansion. Always write a zero to this bit.

TRD

Transfer Request Disable. This bit, when set, causes all data transfers to cease when the Interrupt Status (INT) bit of

the Status Register is set.

0

Transfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.

DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled.

1

Transfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either

PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the

time when TRD is set. After pending requests complete, midscale inputs will be internally generated for the

DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the TRD bit)

will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). The

DMA Current Counter Register will not decrement while both the TRD bit is set and the INT bit is a one.

MCE

Mode Change Enable. This bit must be set whenever the current functional mode of the AD1848K is changed. Specifi-

cally, the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. The

exceptions are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be

cleared at the completion of the desired register changes. The DAC outputs are automatically muted when the MCE bit

is set. After MCE is cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits.

Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to al-

low the reference and all filters to settle. The ADCs will produce midscale values; the DACs’ analog output will be

muted. All converters are internally operating during these

≈128 sample cycles, and the AD1848K will expect playback

data and will generate (midscale capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from

the MCE state regardless of whether or not ACAL was set. ACI will remain HI for these

≈128 sample cycles; system

software should poll this bit rather than count cycles.

Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS)

during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below.

INIT

AD1848K Initialization. This bit is set when the AD1848K is in a state which cannot respond to parallel bus cycles. This

bit is read only.

Immediately after reset and once the AD1848K has left the INIT state, the initial value of this register will be “0100 0000 (40h).”

During AD1848K initialization, this register cannot be written and is always read “1000 0000 (80h).”

Indexed Data Register (ADR1:0 = 1)

ADR1:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1

IXD7

IXD6

IXD5

IXD4

IXD3

IXD2

IXD1

IXD0

IXD7:0

Indexed Register Data. These bits contain the contents of the AD1848K register referenced by the Indexed

Data Register.

During AD1848K initialization. this register cannot be written and is always read as “1000 0000 (80h).”