AD1848K

REV. 0

–20–

Digital Mix Control Register (IXA3:0 = 13)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1 3

DMA5

DMA4

DMA3

DMA2

DMA1

DMA0

res

DME

DME

Digital Mix Enable. This bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the

data from the ADCs are digitally mixed with other data being delivered to the DACs (regardless of whether or not play-

back [PEN] is enabled, i.e., set). If capture is enabled (CEN set) and there is a capture overrun (COR), then the last

sample captured before overrun will be used for the digital mix. If playback is enabled (PEN set) and there is a playback

underrun (PUR), then a midscale zero will be added to the digital mix data.

0

Digital mix disabled (muted)

1

Digital mix enabled

res

Reserved for future expansion. Always write a zero to this bit.

DMA5:0

Digital Mix Attenuation. These bits determine the attenuation of the ADC data in mixing with the DAC input. Each

attenuate step is –1.5 dB ranging to –94.5 dB.

This register’s initial state after reset is “0000 00x0.”

DMA Base Count Registers (IXA3:0 = 14 & 15)

The DMA Base Count Registers in the AD1848K simplify integration of the AD1848K in ISA systems. The ISA DMA controller re-

quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. The programmable DMA Base

Count Registers will allow such interrupts to occur.

The Base Count Registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt

(INT) pin. To load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both

Base Count Registers to load into the Current Count Register. Once AD1848K transfers are enabled, each sample period the Cur-

rent Count Register will decrement until zero count is reached. The next sample period after zero will generate the interrupt and re-

load the Current Count Register with the values in the Base Count Registers. The interrupt is cleared by a write to the Status

Register.

The Host Interrupt Pin (INT) will go HI during the sample period in which the Current Count Register underflows when Interrupt

Enable (IEN) is set. It will go LO when the Interrupt Status (INT) bit is cleared. Note that both the bit and the pin have the same

name (INT). The Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled and also

either the Transfer Request Disable (TRD) bit or the Interrupt Status (INT) bit are zero. Note that the internal INT bit will become

one on counter underflow even if the external interrupt pin is not enabled, i.e., IEN is zero. The Current Count Register is

decremented in both PIO and DMA data transfer modes.

Upper Base Count Register (IXA3:0 = 14)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1 4

UB7

UB6

UB5

UB4

UB3

UB2

UB1

UB0

UB7:0

Upper Base Count. This byte is the upper byte of the base count register containing the eight most significant bits of the

16-bit base register. Reads from this register return the same value which was written. The current count contained in

the counters can not be read.

This register’s initial state after reset is “0000 0000.”

Lower Upper Base Count Register (IXA3:0 = 15)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

1 5

LB7

LB6

LB5

LB4

LB3

LB2

LB1

LB0

LB7:0

Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits of the

16-bit base register. Reads from this register return the same value which was written. The current count contained in

the counters cannot be read.

This register’s initial state after reset is “0000 0000.”