AD1848 datasheet(22/28 Pages) AD

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AD1848K

REV. 0

–22–

For read/capture cycles, the AD1848K will place data on the

DATA7:0 lines while the host is asserting the read strobe, RD,

by holding it LO. For write/playback, the host must place data

on the DATA7:0 pins while strobing the WR signal LO. The

AD1848K latches the write/playback data on the rising edge of

the WR strobe.

When using PIO data transfers, the Status Register must be

polled to determine when data should be transferred. Note that

the ADC capture data will be ready (CRDY HI) from the previ-

ous sample period shortly before the DAC playback data is

ready (PRDY HI) for the next sample period. The user should

not wait for both ADCs and DACs to become ready before initi-

ating data transfers. Instead, as soon as capture data is ready, it

should be read; as soon as the DACs are ready, playback data

should be written.

Values written to the XCTL1:0 bits in the Pin Control Register

(IXA3:0 = 10) will be reflected in the state of the XCTL1:0 ex-

ternal output pins. This feature allows a simple method for sig-

naling or software control of external logic. Changes in state of

the external XCTL pins will occur within one sample period.

Because their change is referenced to the internal sample clock,

no useful timing diagram can be constructed.

Direct Memory Access (DMA) Transfers

The second type of bus cycle supported by the AD1848K are

DMA transfers. Both dual channel and single channel DMA op-

erations are supported. To enable Playback DMA transfers,

playback enable (PEN) must be set and PPIO cleared. To en-

able Capture DMA transfers, capture enable (CEN) must be set

and CPIO cleared. During DMA transfers, the AD1848K as-

serts HI the Capture Data Request (CDRQ) or the Playback

Data Request (PDRQ) followed by the host’s asserting LO the

DMA Capture Data Acknowledge (CDAK) or Playback Data

Acknowledge (PDAK), respectively. The host’s asserted

Acknowledge signals cause the AD1848K to perform DMA

transfers. The input address lines, ADR1:0, are ignored. Data is

transferred between the proper internal sample registers.

The read strobe (RD) and write strobe (WR) delimit valid data

for DMA transfers. Chip select (CS) is a “don’t care”; its state

is ignored by the AD1848K.

The AD1848K asserts the Data Request Signals, CDRQ and

PDRQ, at the rate of once per sample period, where PDRQ is

asserted near the beginning of an internal sample period and

CDRQ is asserted late in the same period to maximize the avail-

able processing time. Once asserted, these signals will remain

active HI until the corresponding DMA cycle occurs with the

host’s Data Acknowledge signals. The Data Request signals will

be deasserted after the falling edge of the final RD or WD strobe

in the transfer of a sample, which typically consists of multiple

bytes. See “Data Ordering” above for a definition of “sample.”

DMA transfers may be independently aborted by resetting the

Capture Enable (CEN) and/or Playback Enable (PEN) bits in

the Interface Configuration Register. The current capture

sample transfer will be completed if a capture DMA is termi-

nated. The current playback sample transfer must be completed

if a playback DMA is terminated. If CDRQ and/or PDRQ are

asserted HI while the host is resetting CEN and/or PEN, the re-

quest must be acknowledged. The host must assert CDAK and/

or PDAK LO and complete a final sample transfer.

Single-Channel DMA

Single-Channel DMA mode allows the AD1848K to be used in

systems with only a single DMA channel. It is enabled by setting

the SDC bit in the Interface Configuration Register. All cap-

tures and playbacks take place on the playback channel. Obvi-

ously, the AD1848K cannot perform a simultaneous capture

and playback in Single-Channel DMA mode.

Playback will occur in single-channel DMA mode exactly as it

does in Two-Channel mode. Capture, however, is diverted to

the playback channel which means that the capture data request

occurs on the PDRQ pin and the capture data acknowledge

must be received on the PDAK pin. The CDRQ pin will remain

inactive LO. Any inputs to CDAK will be ignored.

Playback and capture are distinguished in Single-Channel DMA

mode by the state of the playback enable (PEN) or capture en-

able (CEN) control bits. If both PEN and CEN are set in

Single-Channel DMA mode, playback will be presumed.

To avoid confusion of the origin of a request when switching be-

tween playback and capture in Single-Channel DMA mode,

both CEN and PEN should be disabled and all pending re-

quests serviced before enabling the alternative enable bit.

Switching between playback and capture in Single-Channel

DMA mode no longer requires changing the PPIO and CPIO

bits or passing through the Mode Change Enable state except

for initial setup. For setup, assign zeros to both PPIO and

CPIO. This configures both playback and capture for DMA.

Then, switching between playback and capture can be effected

entirely by setting and clearing the PEN and CEN control bits,

a technique which avoids having to enter the Mode Change

Enable state.

DMA Timing

Below, timing parameters are shown for 8-Bit Mono Sample

Read/Capture and Write/Playback DMA transfers in Figures 13

and 14. Note that in single-channel DMA mode, the Read/

Capture cycle timing shown in Figure 13 applies to the PDRQ

and PDAK signals, rather than the CDRQ and CDAK signals

as shown. The same timing parameters apply to multibyte trans-

fers. The relationship between timing signals is shown in Fig-

ures 15 and 16.

The Host Interrupt Pin (INT) will go HI during the sample

period in which the Current Count Register underflows. This

event is referenced to the internal sample period clock which is

not available externally.

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