AD1848 datasheet(24/28 Pages) AD

24 / 28 page

AD1848K

REV. 0

–24–

DMA Interrupt

Writing to the internal 16-bit Base Count Register sets up the

count value for the number of samples to be transferred. Note

that the number of bytes transferred for a given count will be a

function of the selected global data format. The internal Cur-

rent Count Register is updated with the current contents of the

Upper and Lower Base Count Registers when a write occurs to

the Upper Base Count Register.

The Current Count Register cannot be read by the host. Read-

ing the Base Count Registers will only read back the initializa-

tion values written to them.

The Current Count Register is decremented every sample

period when either the PEN or CEN bit is enabled and also either

the Transfer Request Disable (TRD) bit or the Interrupt Status

(INT) bit is zero. An interrupt event is generated after the Cur-

rent Count Register is zero and an additional playback sample is

transferred. The INT bit in the Status Register always reflects

the current internal interrupt state defined above. The external

INT pin will only go active HI if the Interrupt Enable (IEN) bit

in the Interface Configuration Register is set. If the IEN bit is

zero, the external INT pin will always stay LO, even though the

Status Register’s INT bit may be set.

POWER UP AND RESET

The PWRDWN pin should be held in its active LO state when

power is first applied to the AD1848K. Analog Devices recom-

mends waiting one full second after deasserting PWRDWN be-

fore commencing audio activity with the AD1848K. This will

allow the analog outputs to fully settle to the VREF voltage level

prior to system autocalibration. At any point when powered, the

AD1848K can be put into a state for minimum power consump-

tion by asserting PWRDWN LO. All analog and digital sections

are shut down. The AD1848K’s parallel interface does not func-

tion; all bidirectional signal lines are in high impedance three-

state.

Deasserting PWRDWN by bringing it HI begins the AD1848K’s

initialization. While initializing, the AD1848K ignores all writes

and all reads will yield “1000 0000 (80h).” At the conclusion of

reset initialization, all registers will be set to their default values

as listed in “Control Registers” above. The conclusion of the

initialization period can be detected by polling the index register

for some value other than “1000 0000 (80h).”

It is imperative to autocalibrate on power up for proper opera-

tion. See next section.

AUTOCALIBRATION

The AD1848K can calibrate the ADCs and DACs for greater

accuracy by minimizing DC offsets. Autocalibration occurs

whenever the AD1848K returns from the Mode Change Enable

state and the ACAL bit in the Interface Configuration register

has been set. If the ACAL bit is not set, the RAM normally

containing ADC and DAC offset compensations will be saved,

retaining the offsets of the most recent autocalibration. There-

fore, it is imperative to autocalibrate on power up for proper

operation.

The completion of autocalibration can be determined by polling

the Autocalibrate-In-Progress (ACI) bit in the Test and Initial-

ization Register, which will be set during autocalibration. Trans-

fers enabled during autocalibration do not begin until the

completion of autocalibration.

The following summarizes the procedure for autocalibration:

• Mute left and right DAC outputs, AUX1 and AUX2 inputs,

and digital mix. (It is unnecessary to mute the DAC outputs,

as this will happen automatically.)

• Set the Mode Change Enable (MCE) bit.

• Set the Autocalibration (ACAL) bit.

• Clear the Mode Change Enable (MCE) bit.

• The Autocalibrate-In-Progress (ACI) bit will transition from

LO to HI within five sample periods. It will remain HI for

approximately 384 sample periods. Poll the ACI bit until it

transitions from HI to LO.

• Set to desired gain/attenuation values, and unmute DAC

outputs (if muted), AUX inputs, and digital mix.

During the autocalibration sequence, data output from the

ADCs is meaningless. Inputs to the DACs are ignored. Even if

the user specified the muting of all analog outputs, near the end

of the autocalibration sequence, dc analog outputs very close to

VREF will be produced at the line output.

CHANGING SAMPLE RATES

To change the selection of the current sample rate requires a

Mode Change Enable sequence since the bits which control that

selection are in the Clock and Data Format Register. The fact

that the clocks change requires a special sequence which is sum-

marized as follows:

• If autocalibration will take place at the end of this sequence,

mute the AUX1 and AUX2 inputs and the digital mix.

• Set the Mode Change Enable (MCE) bit.

• In a single write cycle, change the Clock Frequency Divide

Select (CFS2:0) and/or the Clock Source Select (CSS).

• The AD1848K now needs to resynchronize its internal

states to the new clock. Writes to the AD1848K will be

ignored. Reads will produce “1000 0000 (80h)” until the

resynchronization is complete. Poll the Index Register until

something other than this value is returned.

• Clear the Mode Change Enable (MCE) bit.

• If ACAL is set, follow the procedure described in “Auto-

calibration” above.

• Poll the ACI hit until it transitions LO (approximately 128

sample cycles).

• Set to desired gain/attenuation values, and unmute DAC

outputs (if muted).

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