AD1848K

REV. 0

–14–

PIO Data Registers (ADRI :0 = 3)

ADR1:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

3

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0).

Reads will receive data from the PIO Capture Data Register (CD7:0).

During AD1848K initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read

“1000 0000 (80h).”

CD7:0

PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data transfers.

The reading of this register will increment the state machine so that the following read will be from the next appropriate

byte in the sample. The exact byte which is next to be read can be determined by reading the Status Register. Once all

relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is re-

ceived from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the

sample. Until a new sample is received, reads from this register will return the most significant byte of the sample.

PD7:0

PIO Playback Data Register. This is the control register where playback data is written during programmed I/O data

transfers.

Writing data to this register will increment the playback byte tracking state machine so that the following write will be

to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are

ignored. The state machine is reset when the current sample is sent to the DACs.

Indirect Control Register Definitions

The following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed

by a read/write to the Indexed Data Register (ADR1:0 = 1).

Left Input Control (IXA3:0 = 0)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

0

LSS1

LSS0

LMGE

res

LIG3

LIG2

LIG1

LIG0

LIG3:0

Left Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.

res

Reserved for future expansion. Always write a zero to this bit.

LMGE

Left Input Microphone Gain Enable. Setting this bit will enable the +20 dB gain of the left mic input signal.

LSS1:0

Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.

0

Left Line Source Selected

1

Left Auxiliary 1 Source Selected

2

Left Microphone Source Selected

3

Left Line Post-Mixed DAC Output Source Selected

This register’s initial state after reset is “0000 0000.”