AD7714YN datasheet(32/40 Pages) AD

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AD7714

REV. C

–32–

interfaces which require control of the

CS input on the AD7714,

one of the port bits of the 8XC51 (such as P1.1), which is con-

figured as an output, can be used to drive the

CS input.

AD7714

DATA OUT

POL

SYNC

8XC51

RESET

DATA IN

SCLK

P3.0

P3.1

DVDD

Figure 10. AD7714 to 8051 Interface

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7714 should be

connected together. The serial clock on the 8XC51 idles high

between data transfers and, therefore, the POL input of the

AD7714 should be hard-wired to a logic high. The 8XC51

outputs the LSB first in a write operation while the AD7714

expects the MSB first so the data to be transmitted has to be

rearranged before being written to the output serial register.

Similarly, the AD7714 outputs the MSB first during a read

operation while the 8XC51 expects the LSB first. Therefore, the

data that is read into the serial buffer needs to be rearranged

before the correct data word from the AD7714 is available in

the accumulator.

AD7714 to ADSP-2103/ADSP-2105 Interface

Figure 11 shows an interface between the AD7714 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface shown,

the

DRDY bit of the Communications Register is again moni-

tored to determine when the Data Register is updated. The

alternative scheme is to use an interrupt driven system in which

case, the

DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The

RFS and TFS pins of the

ADSP-2103/ADSP-2105 are configured as active low outputs

and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is

also configured as an output. The POL pin of the AD7714 is

hard-wired low. Because the SCLK from the ADSP-2103/

ADSP-2105 is a continuous clock, the

CS of the AD7714 must

be used to gate off the clock once the transfer is complete. The

CS for the AD7714 is active when either the RFS or TFS

outputs from the ADSP-2103/ADSP-2105 are active. The serial

clock rate on the ADSP-2103/ADSP-2105 should be limited to

3 MHz to ensure correct operation with the AD7714.

AD7714

DATA OUT

SYNC

ADSP-2103/2105

RESET

DATA IN

SCLK

RFS

DVDD

TFS

POL

SCLK

Figure 11. AD7714 to ADSP-2103/ADSP-2105 Interface

CODE FOR SETTING UP THE AD7714

Table XV gives a set of read and write routines in C code for

interfacing the 68HC11 microcontroller to the AD7714. The

sample program sets up the various registers on the AD7714

and reads 1000 samples from the part into the 68HC11. The

setup conditions on the part are exactly the same as those out-

lined for the flowchart of Figure 8. In the example code given

here the

DRDY output is polled to determine if a new valid

word is available in the output register.

The sequence of the events in this program are as follows:

1. Write to the Communications Register, setting the channel.

2. Write to the Filter High Register, setting the 4 MSBs of the

filter word and setting the part for 24-bit read, bipolar mode

with boost off.

3. Write to the Filter Low Register, setting the 8 LSBs of the

filter word.

4. Write to the Mode Register, setting the part for a gain of 1,

burnout current off, no filter synchronization and initiating a

self-calibration.

5. Poll the

DRDY Output.

6. Read the data from the Data Register.

7. Loop around doing steps 5 and 6 until the specified number

of samples have been taken.

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