AD7731 datasheet(7/44 Pages) AD

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AD7731

–7–

REV. 0

FASTSTEP™

FILTER

CHOP

ANALOG

INPUT

DIGITAL

OUTPUT

BUFFER

SKIP

OUTPUT

SCALING

22-TAP

FIR FILTER

THE ANALOG INPUT TO THE PART

CAN BE CHOPPED. IN CHOPPING MODE,

THE INPUT IS CHOPPEDAND THE OUTPUT OF

THE FIRST STAGE FILTER IS CHOPPED

REMOVING ERRORS IN THAT PATH.

THE DEFAULT CONDITION IS

CHOPPING DISABLED

THE FIRST STAGE OF THE DIGITAL

FILTERING ON THE PART IS THE

SINC3 FILTER. THE OUTPUT UPDATE

RATE AND BANDWIDTH OF THIS

FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC3 FILTER IS

THE ONLY FILTERING PERFORMED

ON THE P3T.

IN SKIP MODE, THERE IS NO

SECOND STAGE OF FILTERING ON

THE PART. THE SINC3 FILTER IS

THE ONLY FILTERING PERFORMED

ON THE PART. THIS IS THE

SECOND STAGE FILTER

WITH SKIP DISABLED, THE NORMAL

OPERATING MODE OF THE SECOND STAGE

OF THE DIGITAL FILTERING ON THE PART IS

A FIXED 22-TAP FIR FILTER. IN SKIP MODE,

THIS FIR FILTER IS BYPASSED. WHEN

FASTSTEP™ MODE IS ENABLED AND A

STEP INPUT IS DETECTED, THE SECOND

STAGE FILTERING IS PERFORMED BY THE

FAST STEP FILTER UNTIL THE OUTPUT OF

THIS FILTER HAS FULLY SETTLED

THE OUTPUT WORD FROM THE

DIGITAL FILTER IS SCALED BY THE

CALIBRATION COEFFICIENTS

BEFORE BEING PROVIDED AS THE

CONVERSION RESULT

WHEN FASTSTEP™ MODE IS

ENABLED AND A STEP CHANGE ON

THE INPUT HAS BEEN DETECTED,

THE SECOND STAGE FILTERING IS

PERFORMED BY THE FASTSTEP™

FILTER UNTIL THE FIR FILTER HAS

FULLY SETTLED.

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. THE DEFAULT

CONDITION IS CHOPPING

DISABLED

THE PROGRAMMABLE GAIN

CAPABILITY OF THE PART IS

INCORPORATED AROUND THE

SIGMA DELTA MODULATOR.THE

MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED

TO THE SAMPLING CAPACITOR OF

THE SIGMA DELTA MODULATOR.

THIS ISOLATES THE SAMPLING

CAPACITOR CHARGING CURRENTS

FROM THE ANALOG INPUT PINS

PGA &

SIGMA-DELTA

MODULATOR

SINC3

FILTER

CHOP

INPUT CHOPPING

SINC3 FILTER

SKIP MODE

22-TAP FIR FILTER

OUTPUT SCALING

FASTSTEP™ FILTER

OUTPUT CHOPPING

PGA & SIGMA-DELTA

MODULATOR

BUFFER

SEE PAGE 25

SEE PAGE 26

SEE PAGE 29

SEE PAGE 28

SEE PAGE 25

SEE PAGE 24

SEE PAGE 23

Figure 3. Signal Processing Chain

PIN CONFIGURATION

SCLK

MCLK IN

DGND

DVDD

SYNC

RDY

MCLK OUT

POL

DIN

DOUT

AGND

AVDD

AIN5

AIN1

STANDBY

817

916

TOP VIEW

(Not to Scale)

AD7731

RESET

REF IN(–)

REF IN(+)

AIN2

AIN3/D1

AIN4/D0

AIN6

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

SCLK

Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer

serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a

continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-

mitted to or from the AD7731 in smaller batches of data.

MCLK IN

Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock.

A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN

pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified

with a clock input frequency of 4.9152 MHz.

AD7731 Datasheet(PDF) 7 Page - Analog Devices

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