AD7851ARS datasheet(14/36 Pages) AD

14 / 36 page

AD7851

–14–

REV. A

CIRCUIT INFORMATION

The AD7851 is a fast, 14-bit single supply A/D converter. The

part requires an external 6/7 MHz master clock (CLKIN), two

CREF capacitors, a CONVST signal to start conversion and

power supply decoupling capacitors. The part provides the user

with track/hold, on-chip reference, calibration features, A/D

converter and serial interface logic functions on a single chip.

The A/D converter section of the AD7851 consists of a conven-

tional successive-approximation converter based around a ca-

pacitor DAC. The AD7851 accepts an analog input range of

0 V to +VDD where the reference can be tied to VDD. The refer-

ence input to the part is buffered onchip.

A major advantage of the AD7851 is that a conversion can be

initiated in software as well as applying a signal to the CONVST

pin. Another innovative feature of the AD7851 is self-calibration

on power-up, which is initiated having a 0.01

µF capacitor from

the CAL pin to AGND, to give superior dc accuracy. The part

should be allowed 150 ms after power-up to perform this auto-

matic calibration before any reading or writing takes place. The

part is available in a 24-pin SSOP package and this offers the user

considerable space saving advantages over alternative solutions.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7851 by pulsing the

CONVST

input or by writing to the control register and setting

the CONVST bit to 1. On the rising edge of CONVST (or at

the end of the control register write operation), the on-chip

track/hold goes from track to hold mode. The falling edge of the

CLKIN signal which follows the rising edge of the edge of

CONVST

signal initiates the conversion, provided the rising

edge of CONVST occurs at least 10 ns typically before this

CLKIN edge. The conversion cycle will take 18.5 CLKIN peri-

ods from this CLKIN falling edge. If the 10 ns setup time is

AVDD

DVDD

AIN(+)

AIN(–)

AMODE

CREF1

CREF2

SLEEP

DIN

DOUT

SYNC

SM1

SM2

CONVST

AGND

DGND

CLKIN

SCLK

REFIN/REFOUT

POLARITY

AD7851

ANALOG (5V)

SUPPLY

0.01µF

0.1µF

10µF

DVDD

UNIPOLAR RANGE

0.01µF

47nF

SERIAL MODE

SELECTION BITS

MASTER

CLOCK

INPUT

CONVERSION

START INPUT

FRAME SYNC OUTPUT

SERIAL DATA OUTPUT

0.01µF

CAL

AUTO CAL ON

POWER-UP

INTERNAL

REFERENCE

0V TO VREF

INPUT

7MHz/6MHz

OSCILLATOR

SERIAL CLOCK OUTPUT

DVDD

333kHz/285kHz PULSE

GENERATOR

OPTIONAL

EXTERNAL

REFERENCE

AD1584/REF198

0.01µF

ANALOG (5V)

SUPPLY

0.1µF

10µF

DIN AT DGND

=> NO WRITING

TO DEVICE

0.01µF

470nF

CH1

CH2

CH3

CH4

OSCILLOSCOPE

2 LEADING ZEROS

FOR ADC DATA

Figure 10. Typical Circuit

not met, the conversion will take 19.5 CLKIN periods. The

maximum specified conversion time is 3.25

µs (6 MHz ) and

2.8

µs (7 MHz) for the A and K Grades respectively for the

AD7851 (19.5 tCLKIN, CLKIN = 6/7 MHz). When a conversion

is completed, the BUSY output goes low, and then the result of

the conversion can be read by accessing the data through the se-

rial interface. To obtain optimum performance from the part,

the read operation should not occur during the conversion or

500 ns prior to the next CONVST rising edge. However, the

maximum throughput rates are achieved by reading/writing dur-

ing conversion, and reading/writing during conversion is likely

to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The

AD7851 can operate at throughput rates up to 333 kHz. For the

AD7851 a conversion takes 19.5 CLKIN periods, 2 CLKIN

periods are needed for the acquisition time giving a full cycle

time of 3.59

µs (= 279 kHz, CLKIN = 6 MHz) for the K grade

and 3.08

µs (= 325 kHz, CLKIN = 7 MHz) for the A grade.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7851.

The DIN line is tied to DGND so that no data is written to the

part. The AGND and the DGND pins are connected together

at the device for good noise suppression. The CAL pin has a

0.01

µF capacitor to enable an automatic self-calibration on

power-up. The SCLK and SYNC are configured as outputs by

having SM1 and SM2 at DVDD. The conversion result is output

in a 16-bit word with 2 leading zeros followed by the MSB of

the 14-bit result. Note that after the AVDD and DVDD power-up,

the part will require 150 ms for the internal reference to settle

and for the automatic calibration on power-up to be completed.

For applications where power consumption is a major concern,

the SLEEP pin can be connected to DGND. See Power-Down

section for more detail on low power applications.

AD7851ARS Datasheet(PDF) 14 Page - Analog Devices

AD7851ARS Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL