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AD7851ARS Datasheet(PDF) 31 Page - Analog Devices |
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AD7851ARS Datasheet(HTML) 31 Page - Analog Devices |
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31 / 36 page  –31– REV. A AD7851 AD7851 to ADSP-21xx Interface Figure 47 shows the AD7851 interface to the ADSP-21xx. The ADSP-21xx is the slave and the AD7851 is the master. The AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in the serial port control register should be set up as TFSR = RFSR = 1 (need a frame sync for every transfer), SLEN = 15 (16-bit word length), TFSW = RFSW = 1 (alternate framing mode for transmit and receive operations), INVRFS = INVTFS = 1 (active low RFS and TFS), IRFS = ITFS = 0 (External RFS and TFS), and ISCLK = 0 (external serial clock). The CLKIN and CONVST signals could be supplied from the ADSP-21xx or from an external source. The AD7851 supplies the SCLK and the SYNC signals to the ADSP-21xx and the reading and writing takes place during conversion. The BUSY signal only indicates when the conversion is finished and may not be required. The data access and hold times of the ADSP- 21xx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz with a 5 V supply. AD7851 CONVST CLKIN SCLK DOUT BUSY SM1 SM2 POLARITY OPTIONAL 7MHz/6MHz SYNC RFS DIN AT DGND FOR NO WRITING TO PART SLAVE MASTER OPTIONAL DIN DVDD OPTIONAL IRQ DT TFS ADSP-21xx DR SCK Figure 47. ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface. Here the DSP5600x is the master and the AD7851 is the slave. The AD7851 is in Interface Mode 3. The setting of the bits in the registers of the DSP5600x would be for synchronous opera- tion (SYN = 1), internal frame sync (SCD2 = 1), Internal clock (SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames sync only active at beginning of the transfer (FSL1 = 0, FSL0 = 1). A gated clock can be used (GCK = 1) or if the SCLK is to be tied to the CLKIN of the AD7851, then there must be a con- tinuous clock (GCK = 0). Again the data access and hold times of the DSP5600x and the AD7851 should allow for an SCLK of 7 MHz/6 MHz. AD7851 CONVST CLKIN SCLK DOUT BUSY SM1 SM2 POLARITY OPTIONAL 7MHz/6MHz SYNC DIN AT DGND FOR NO WRITING TO PART SLAVE OPTIONAL DIN DVDD OPTIONAL DSP 56000/1/2/L002 SRD SCK SC2 MASTER IRQ STD Figure 48. DSP56000/1/2 Interface AD7851 to TMS320C20/25/5x/LC5x Interface Figure 49 shows the AD7851 to the TMS320Cxx interface. The AD7851 is the master and operates in Interface Mode 5. For the TMS320Cxx the CLKX, CLKR, FSX, and FSR pins should all be configured as inputs. The CLKX and the CLKR should be connected together as should the FSX and FSR. Since the AD7851 is the master and the reading and writing occurs during the conversion, the BUSY only indicates when the con- version is finished and thus may not be required. Again the data access and hold times of the TMS320Cxx and the AD7851 al- lows for a CLKIN of 7 MHz/6 MHz. AD7851 CONVST CLKIN SCLK DOUT BUSY SM1 SM2 POLARITY OPTIONAL 7MHz/6MHz SYNC DIN AT DGND FOR NO WRITING TO PART SLAVE MASTER OPTIONAL DIN DVDD OPTIONAL DT FSX INT0 TMS320C20/ 25/5x/LC5x DR CLKR FSR CLKX Figure 49. TMS320C20/25/5x Interface |
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