AD7851

–24–

REV. A

DB15

DB0

DB0

DB15

t

3

DIN (I/O)

t

3

t

11

t

6

116

16

1

t

5A

t

12

DIN BECOMES AN INPUT

3-STATE

t

6

t

11

DIN BECOMES AN OUTPUT

t

t

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

SCLK (I/P)

t

8

t

14

t

7

DATA WRITE

DATA READ

Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)

DB15

DB0

DB0

DB15

DIN (I/O)

t

t

6

116

16

1

t

13

t

6

DIN BECOMES AN INPUT

t

6

POLARITY PIN

LOGIC HIGH

SCLK (I/P)

t

8

t

14

t

7

DATA WRITE

DATA READ

Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low

(i.e., Interface Mode 1, SM1 = SM2 = 0)

DETAILED TIMING SECTION

MODE 1 (2-Wire 8051 Interface)

The read and writing takes place on the DIN line and the con-

version is initiated by pulsing the CONVST pin (note that in

every write cycle the 2/3 MODE bit must be set to 1). The con-

version may be started by setting the CONVST bit in the con-

trol register to 1 instead of using the CONVST line.

Below in Figure 33 and in Figure 34 are the timing diagrams for

Interface Mode 1 in Table XI where we are in the 2-wire inter-

face mode. Here the DIN pin is used for both input and output

as shown. The SYNC input is level triggered active low and can

be pulsed (Figure 33) or can be constantly low (Figure 34).

In Figure 33 the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK the DIN is con-

figured as an output. When the SYNC is taken high the DIN is

3-stated. Taking SYNC low disables the 3-state on the DIN pin

and the first SCLK falling edge clocks out the first data bit.

Once the 16 clocks have been provided the DIN pin will auto-

continuous SCLK shown by the dotted waveform in Figure 33

can be used provided that the SYNC is low for only 16 clock

pulses in each of the read and write cycles. The POLARITY pin

may be used to change the SCLK edge which the data is

sampled on and clocked out on.

In Figure 34 the SYNC line is tied low permanently and this re-

sults in a different timing arrangement. With SYNC tied low

permanently the DIN pin will never be 3-stated. The 16th rising

edge of SCLK configures the DIN pin as an input or an output

as shown in the diagram. Here no more than 16 SCLK pulses

must occur for each of the read and write operations.

If reading from and writing to the calibration registers in this in-

terface mode, all the selected calibration registers must be read

from or written to. The read and write operations cannot be

aborted. When reading from the calibration registers, the DIN

pin will remain as an output for the full duration of all the cali-

bration register read operations. When writing to the calibration

registers, the DIN pin will remain as an input for the full dura-

tion of all the calibration register write operations.