AD9777EB datasheet(18/48 Pages) AD

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AD9777

tDS

tSCLK

tPWH

tPWL

tDS

tDH

INSTRUCTION BIT 7

INSTRUCTION BIT 6

SCLK

SDIO

Figure 4. Timing Diagram for Register Write to AD9777

tDV

DATA BIT N

DATA BIT N–1

SCLK

SDIO

SDO

Figure 5. Timing Diagram for Register Read from AD9777

NOTES ON SERIAL PORT OPERATION

The AD9777 serial port configuration bits reside in Bits 6 and 7

of Register Address 00h. It is important to note that the configura-

tion changes immediately upon writing to the last bit of the register.

For multibyte transfers, writing to this register may occur during

the middle of the communication cycle. Care must be taken to

compensate for this new configuration for the remaining bytes

of the current communication cycle.

The same considerations apply to setting the reset bit in Register

Address 00h. All other registers are set to their default values, but

the software reset doesn’t affect the bits in Register Address 00h.

It is recommended to use only single byte transfers when chang-

ing serial port configurations or initiating a software reset.

A write to Bits 1, 2, and 3 of Address 00h with the same logic

levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows

the user to reprogram a lost serial port configuration and to reset

the registers to their default values. A second write to Address

00h with reset bit low and serial port configuration as specified

above (XY) reprograms the OSC IN multiplier setting. A changed

fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles

(equals wake-up time).

DAC OPERATION

The dual 16-bit DAC output of the AD9777, along with the

reference circuitry, gain, and offset registers, is shown in Figure 6.

Referring to the transfer functions in Equation 1, a reference

current is set by the internal 1.2 V reference, the external RSET

resistor, and the values in the coarse gain register. The fine gain

DAC subtracts a small amount from this and the result is input

to IDAC and QDAC, where it is scaled by an amount equal to

1024/24. Figures 7a and 7b show the scaling effect of the coarse

and fine adjust DACs. IDAC and QDAC are PMOS current

source arrays, segmented in a 5-4-7 configuration. The five

most significant bits control an array of 31 current sources. The

next four bits consist of 15 current sources whose values are all

equal to 1/16 of an MSB current source. The seven LSBs are

binary weighted fractions of the middle bit’s current sources. All

current sources are switched to either IOUTA or IOUTB, depend-

ing on the input code.

The fine adjustment of the gain of each channel allows for

improved balance of QAM modulated signals, resulting in

improved modulation accuracy and image rejection. In the

Applications section of this data sheet, performance data is

included that shows to what degree image rejection can be

improved when the AD9777 is used with an AD8345 quadra-

ture modulator from ADI.

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