AD9833 datasheet(12/18 Pages) AD

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AD9833

–12–

REV PrG

PRELIMINARY TECHNICAL DATA

appear at the DAC output 7 MCLK cycles after RESET is

set to 0.

Table 9: Applying RESET

RESET bit

Result

No Reset Applied

Internal Registers Reset

The Sleep Function

Sections of the AD9833 which are not in use can be pow-

ered down to minimise power consumption. This is done

using the Sleep Function. The parts of the chip that can

be powered down are the Internal clock and the DAC.

The bits required for the Sleep Function are outlined in

Table 10.

Table 10: Applying the SLEEP Function

SLEEP1

SLEEP12

Result

bit

No powerdown

DAC Powered Down

Internal Clock disabled

Both the DAC powered down and

the Internal Clock disabled

DAC Powered Down: This is useful when the AD9833 is

used to output the MSB of the DAC data only. In this

case, the DAC is not required so it can be powered down

to reduce power consumption.

Internal Clock disabled: When the internal clock of the

AD9833 is disabled the DAC output will remain at its

present value as the NCO is no longer accumulating. New

frequency, phase and control words can be written to the

part when the SLEEP1 control bit is active. The

synchronising clock is still active which means that the

selected frequency and phase registers can also be changed

using the control bits. Setting the SLEEP1 bit equal to 0

enables the MCLK. Any changes made to the registers

while SLEEP1 was active will be seen at the output after a

certain latency.

The VOUT Pin

The AD9833 offers a variety of outputs from the chip, all

of which are available from the VOUT pin. The choice of

outputs are:

The MSB of the DAC data,

A sinusoidal output or

A ramp output.

The bits OPBITEN (D5) and MODE (D1) in the control

the AD9833. This is explained further below and also in

Table 11.

MSB of the DAC data: The MSB of the DAC data can be

output from the AD9833. By setting the OPBITEN (D5)

control bit to 1, the MSB of the DAC data is available at

the VOUT pin. This is useful as a coarse clock source.

This square wave can also be divided by 2 before being

output. The bit DIV2 (D3) in the control register controls

the frequency of this output from the VOUT pin.

Sinusoidal Output: The SIN ROM is used to convert the

phase information from the frequency and phase registers

into amplitude information which results in a sinusoidal

signal at the output. To have a sinusoidal output from the

VOUT pin, set the bit MODE (D1) = 0 and the

OPBITEN (D5) bit to 0.

Up/Down Ramp Output: The SIN ROM can be bypassed

so that the truncated digital output from the NCO is sent

to the DAC. In this case, the output is no longer sinusoi-

dal.

The DAC will produce a ramp up/down function. To

have a ramp output from the VOUT pin set the bit

MODE (D1) = 1.

Note that the SLEEP12 bit must be 0 (i.e. the DAC is

enabled) when using this pin.

Table 11: Various Outputs from VOUT

OPBITEN

MODE

DIV2

VOUT

bit

Sinusoid

Up/Down Ramp

DAC data MSB / 2

DAC data MSB

Reserved

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