AD9833

–4–

REV PrG

PRELIMINARY TECHNICAL DATA

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND

. . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

VDD to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

AGND to DGND. . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V

Digital I/O Voltage to DGND . –0.3 V to VDD + 0.3 V

Analog I/O Voltage to AGND . –0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . –65°C to +150°C

PIN CONFIGURATION

Maximum Junction Temperature . . . . . . . . . . . . . . 150°C

µSOIC Package

θ

θ

. . . . . . . . . . . . . . . . . . . 44°C/W

Lead Temperature, Soldering (10 sec)

. . . . . . . . . 300°C

IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9833BRM

– 40°C to +85°C

14-Pin

µSOIC

(Micro Small Outline IC )

RM-10

EVAL-AD9833EB

Evaluation Board

1

2

3

4

5

6

7

8

TOP VIEW

(Not to Scale)

VDD

CAP/2.5V

DGND

MCLK

VOUT

AGND

FSYNC

SCLK

SDATA

AD9833

10

9

COMP

PIN DESCRIPTION

Pin #

Mnemonic

Function

POWER SUPPLY

2

V D D

Positive power supply for the analog section and the digital interface sections.

The on board 2.5 V

regulator is also supplied from VDD. VDD can have a value from +2.3 V to +5.5 V. A 0.1 µF and

10 µF decoupling capacitor should be connected between VDD and AGND.

3

CAP/2.5V

The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from VDD

using an on board regulator (when VDD exceeds +2.7 V). The regulator requires a decoupling

capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If VDD is equal to

or less than +2.7 V, CAP/2.5V should be tied directly to VDD.

4

DGND

Digital Ground.

9

AGND

Analog Ground.

ANALOG SIGNAL AND REFERENCE

1

COMP

A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.

10

VOUT

Voltage Output. The analog and digital output from the AD9833 is available at this pin.

An

external load resistor is not required as the device has a 200W resistor on board.

DIGITAL INTERFACE AND CONTROL

5

MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of

MCLK. The output frequency accuracy and phase noise are determined by this clock.

6

SDATA

Serial Data Input. The 16-bit serial data word is applied to this input.

7

SCLK

Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.

8

FSYNC

Active Low Control Input. This is the frame synchronisation signal for the input data. When

FSYNC is taken low, the internal logic is informed that a new word is being loaded into the

device.