AD9833

–3–

REV PrG

PRELIMINARY TECHNICAL DATA

Parameter

Units

Test Conditions/Comments

40

ns min

MCLK Period

16

ns min

MCLK High Duration

16

ns min

MCLK Low Duration

25

ns min

SCLK Period

10

ns min

SCLK High Duration

10

ns min

SCLK Low Duration

5

ns min

FSYNC

 to SCLK Falling Edge Setup Time

10

ns min

FSYNC to SCLK Hold Time

ns max

5

ns min

Data Setup Time

3

ns min

Data Hold Time

Figure 2. Master Clock

Figure 3. Serial Timing

MCLK

SCLK

FSYNC

SDATA

D15

D14

D2

D1

D0

D15

D14

Figure 1. Test Circuit With which Specifications are tested.

VOUT

COMP

12

AD9833

10-BIT DAC

SIN

ROM

20pF

10nF

VDD

REGULATOR

100nF

CAP/2.5V

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9833 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.