AD9833 datasheet(15/18 Pages) AD

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AD9833

– 15–

REV PrG

PRELIMINARY TECHNICAL DATA

Figure 8. Data Writes

INTERFACING TO MICROPROCESSORS

The AD9833 has a standard serial interface which allows

the part to interface directly with several microprocessors.

The device uses an external serial clock to write the data/

control information into the device. The serial clock can

have a frequency of 40 MHz maximum. The serial clock

can be continuous or, it can idle high or low between

write operations. When data/control information is being

written to the AD9833, FSYNC is taken low and is held

low while the 16 bits of data are being written into the

AD9833. The FSYNC signal frames the 16 bits of infor-

mation being loaded into the AD9833.

AD9833 to ADSP-21xx Interface

Figure 9 shows the serial interface between the AD9833

and the ADSP-21xx. The ADSP-21xx should be set up to

operate in the SPORT Transmit Alternate Framing Mode

(TFSW = 1).

The ADSP-21xx is programmed through

the SPORT control register and should be configured as

follows:

Internal clock operation (ISCLK = 1)

Active low framing (INVTFS = 1)

16-bit word length (SLEN = 15)

Internal frame sync signal (ITFS = 1)

Generate a frame sync for each write (TFSR = 1).

Transmission is initiated by writing a word to the Tx reg-

ister after the SPORT has been enabled. The data is

clocked out on each rising edge of the serial clock and

clocked into the AD9833 on the SCLK falling edge.

ADSP-2101/

ADSP-2103*

AD9833*

TFS

SCLK

FSYNC

* ADDITIONAL PINS OMITTED FOR CLARITY

SDATA

SCLK

Figure 9. ADSP2101/ADSP2103 to AD9833 Interface

AD9833 to 68HC11/68L11 Interface

Figure 10 shows the serial interface between the AD9833

and the 68HC11/68L11 microcontroller. The

microcontroller is configured as the master by setting bit

MSTR in the SPCR to 1 and, this provides a serial clock

on SCK while the MOSI output drives the serial data line

SDATA. Since the microcontroller does not have a dedi-

cated frame sync pin, the FSYNC signal is derived from a

port line (PC7). The set up conditions for correct opera-

tion of the interface are as follows:

DATA WRITE

WRITE A FULL 28-BIT WORD

TO A FREQUENCY REGISTER?

WRITE 14 MSBs OR LSBs

TO A FREQUENCY REGISTER?

WRITE TO PHASE

(CONTROL REGISTER WRITE)

B28 (D13) = 1

WRITE 2 CONSECUTIVE

16-BIT WORDS

(See Table 5 for Example)

WRITE A 16-BIT WORD

(See Tables 6 & 7 for

examples)

(CONTROL REGISTER WRITE)

B28 (D13) = 0

HLB (D12) = 0 / 1

WRITE ANOTHER FULL

28 BITS TO A

FREQUENCY REGISTER?

WRITE 14 MSBs OR LSBs

TO A

FREQUENCY REGISTER?

(16 - Bit Write)

D15, D14 = 11

D13 = 0/1 (chooses the

phase register)

D12 = X

D11 ... D0 = Phase Data

WRITE TO ANOTHER

PHASE REGISTER?

YES

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