ADSP-2104 datasheet(27/36 Pages) AD

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ADSP-2104/ADSP-2109

REV. 0

–27–

TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the

processor operates correctly with other devices.

MEMORY REQUIREMENTS

The table below shows common memory device specifications

and the corresponding ADSP-2104L/ADSP-2109L timing

parameters, for your convenience.

GENERAL NOTES

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

ADSP-2104L/ADSP-2109L

Memory Specification

Timing Parameter

Timing Parameter Definition

Address Setup to Write Start

tASW

A0–A13, DMS, PMS Setup before WR Low

Address Setup to Write End

tAW

A0–A13, DMS, PMS Setup before WR Deasserted

Address Hold Time

tWRA

A0–A13, DMS, PMS Hold after WR Deasserted

Data Setup Time

tDW

Data Setup before WR High

Data Hold Time

tDH

Data Hold after WR High

OE to Data Valid

tRDD

RD Low to Data Valid

Address Access Time

tAA

A0–A13, DMS, PMS, BMS to Data Valid

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