ADSP-2104 datasheet(3/36 Pages) AD

3 / 36 page

ADSP-2104/ADSP-2109

REV. 0

–3–

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109

architecture. The processor contains three independent compu-

tational units: the ALU, the multiplier/accumulator (MAC), and

the shifter. The computational units process 16-bit data directly

and have provisions to support multiprecision computations.

The ALU performs a standard set of arithmetic and logic

operations; division primitives are also supported. The MAC

performs single-cycle multiply, multiply/add, and multiply/

subtract operations. The shifter performs logical and arithmetic

shifts, normalization, denormalization, and derive exponent

operations. The shifter can be used to efficiently implement

numeric format control including multiword floating-point

representations.

The internal result (R) bus directly connects the computational

units so that the output of any unit may be used as the input of

any unit on the next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient use of these computational units.

The sequencer supports conditional jumps, subroutine calls,

and returns in a single cycle. With internal loop counters and

loop stacks, the ADSP-2104/ADSP-2109 executes looped code

with zero overhead—no explicit jump instructions are required

to maintain the loop. Nested loops are also supported.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one of

four modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers. The circular buffering feature is also used by

the serial ports for automatic data transfers to (and from) on-

chip memory.

Efficient data transfer is achieved with the use of five internal

buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA, DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD, DMD) share a single external data bus.

The BMS, DMS, and PMS signals indicate which memory

space is using the external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-2104/ADSP-2109 to fetch two operands in a

single cycle, one from program memory and one from data

memory. The processor can fetch an operand from on-chip

program memory and the next instruction in the same cycle.

The memory interface supports slow memories and memory-

mapped peripherals with programmable wait state generation.

External devices can gain control of the processor’s buses with

the use of the bus request/grant signals (BR, BG).

One bus grant execution mode (GO Mode) allows the ADSP-

2104/ADSP-2109 to continue running from internal memory.

A second execution mode requires the processor to halt while

buses are granted.

Figure 1. ADSP-2104/ADSP-2109 Block Diagram

R Bus

DMD BUS

PMD BUS

DMA BUS

PMA BUS

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BOOT

ADDRESS

GENERATOR

TIMER

BUS

EXCHANGE

COMPANDING

CIRCUITRY

DMA BUS

PMA BUS

DMD BUS

PMD BUS

PROGRAM

SEQUENCER

INSTRUCTION

PROGRAM

MEMORY

SRAM

or ROM

DATA

MEMORY

SRAM

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

INPUT REGS

OUTPUT REGS

SHIFTER

INPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

RECEIVE REG

TRANSMIT REG

SERIAL

PORT 0

MUX

RECEIVE REG

TRANSMIT REG

SERIAL

PORT 1

ADSP-2104 Datasheet(PDF) 3 Page - Analog Devices

ADSP-2104 Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL