ADV7175 datasheet(19/36 Pages) AD

19 / 36 page

ADV7175/ADV7176

REV. A

–19–

SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0)

(Address (SR4–SR0) = 05H–02H)

These 8-bit wide registers are used to set up the subcarrier fre-

quency. The value of these registers are calculated by using the

following equation:

Subcarrier Frequency Register =

232 –1

FCLK

* FSCF

i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5796 MHz

Subcarrier Frequency Register =

232 –1

×106

* 3.579545

×106

Subcarrier Frequency Register = 21F07C16 HEX

Figure 33 shows how the frequency is set up by the 4 registers.

SUBCARRIER

FREQUENCY

REG 0

SUBCARRIER

FREQUENCY

REG 1

SUBCARRIER

FREQUENCY

REG 2

SUBCARRIER

FREQUENCY

REG 3

FSC6

FSC5

FSC3

FSC1

FSC4

FSC2

FSC0

FSC7

FSC30 FSC29

FSC27

FSC25

FSC28

FSC26

FSC24

FSC31

FSC22 FSC21

FSC19

FSC17

FSC20

FSC18

FSC16

FSC23

FSC14 FSC13

FSC11

FSC9

FSC12

FSC10

FSC8

FSC15

Figure 33. Subcarrier Frequency Register

SUBCARRIER PHASE REGISTER (FP7–FP0):

(Address (SR4–SR0) = 06H)

This 8-bit wide register is used to set up the subcarrier phase.

Each bit represents 1.41

°.

TIMING REGISTER 0 (TR07–TR00)

(Address (SR4-SR0) = 07H)

Timing Register 0 is a 8-bit wide register.

Figure 34 shows the various operations under the control of

Timing Register 0. This register can be read from as well

written to.

TIMING REGISTER 0 (TR07–TR00)

BIT DESCRIPTION

Master/Slave Control (TR00)

This bit controls whether the ADV7175/ADV7176 is in master

or slave mode.

Timing Mode Control (TR02–TR01)

These bits control the timing mode of the ADV7175/ADV7176

These modes are described in the Timing and Control section

of the data sheet.

BLANK

Control (TR03)

This bit controls whether the BLANK input is used when the

part is in slave mode.

Luma Delay Control (TR05–TR04)

These bits control the addition of a luminance delay. Each bit

represents a delay of 74 ns.

Pixel Port Select (TR06)

This bit is used to set the pixel port to accept 8-bit or 16-bit

data. If an 8-bit input is selected the data will be set up on

Pins P7–P0.

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the inter-

nal timing counters. This bit should be toggled after setting up a

new timing mode.

TR01

TR00

TR07

TR02

TR03

TR05

TR06

TR04

TIMING

TR07

BLACK INPUT

CONTROL

ENABLE

DISABLE

TR03

PIXEL PORT

CONTROL

8-BIT

16-BIT

TR06

MASTER/SLAVE

CONTROL

SLAVE TIMING

MASTER TIMING

TR00

LUMA DELAY

0ns DELAY

74ns DELAY

148ns DELAY

222ns DELAY

TR05 TR04

TIMING MODE

SELECTION

MODE 0

MODE 1

MODE 2

MODE 3

TR02 TR01

Figure 34. Timing Register 0

ADV7175 Datasheet(PDF) 19 Page - Analog Devices

ADV7175 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL