LTC3589 datasheet(20/36 Pages) LINER

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LTC3375

3375fa

For more information www.linear.com/3375

operaTion

tSU, DAT

tHD, STA

tHD, DAT

SDA

SCL

tSU, STA

tHD, STA

tSU, STO

3375 F03

tBUF

tLOW

tHIGH

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

tSP

ACK

ADDRESS

ACK

STOP

START

SDA

SCL

DATA BYTE A

DATA BYTE B

Figure 3. I2C Bus Operation

I2C Interface

TheLTC3375maycommunicatewithabusmasterusingthe

standardI2C2-wireinterface.Thetimingdiagram(Figure 3)

shows the relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is

not in use. External pull-up resistors or current sources,

such as the LTC1694 SMBus accelerator, are required

on these lines. The LTC3375 is both a slave receiver and

slave transmitter. The I2C control signals, SDA and SCL

are scaled internally to the VCC supply.

The I2C port has an undervoltage lockout on the VCC pin.

When VCC is below 1.8V, the I2C serial port is cleared and

theLTC3375registersaresettotheirdefaultconfigurations.

I2C Bus Speed

The I2C port is designed to be operated at speeds of up

to 400kHz. It has built-in timing delays to ensure cor-

rect operation when addressed from the I2C compatible

master device.

I2C Start and Stop Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3375,themastermaytransmitaSTOPconditionwhich

commands the LTC3375 to act upon its new command

set. A STOP condition is sent by the master by transition-

ing SDA from LOW to HIGH while SCL is HIGH. The bus

is then free for communication with another I2C device.

I2C Byte Format

Each byte sent to or received from the LTC3375 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3375

most significant bit (MSB) first.

I2C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3375 is written

to (write address), it acknowledges its write address as

well as the subsequent two data bytes. When it is read

from (read address), the LTC3375 acknowledges its read

address only. The bus master should acknowledge receipt

of information from the LTC3375.

An acknowledge (active LOW) generated by the LTC3375

letsthemasterknowthatthelatestbyteofinformationwas

received.Theacknowledgerelatedclockpulseisgenerated

by the master. The master releases the SDA line (HIGH)

during the acknowledge clock cycle. The LTC3375 pulls

down the SDA line during the write acknowledge clock

pulse so that it is a stable LOW during the HIGH period

of this clock pulse.

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